cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sysfs-class-iommu-intel-iommu (1037B)

      1What:		/sys/class/iommu/<iommu>/intel-iommu/address
      2Date:		June 2014
      3KernelVersion:	3.17
      4Contact:	Alex Williamson <alex.williamson@redhat.com>
      5Description:
      6		Physical address of the VT-d DRHD for this IOMMU.
      7		Format: %llx.  This allows association of a sysfs
      8		intel-iommu with a DMAR DRHD table entry.
      9
     10What:		/sys/class/iommu/<iommu>/intel-iommu/cap
     11Date:		June 2014
     12KernelVersion:	3.17
     13Contact:	Alex Williamson <alex.williamson@redhat.com>
     14Description:
     15		The cached hardware capability register value
     16		of this DRHD unit.  Format: %llx.
     17
     18What:		/sys/class/iommu/<iommu>/intel-iommu/ecap
     19Date:		June 2014
     20KernelVersion:	3.17
     21Contact:	Alex Williamson <alex.williamson@redhat.com>
     22Description:
     23		The cached hardware extended capability register
     24		value of this DRHD unit.  Format: %llx.
     25
     26What:		/sys/class/iommu/<iommu>/intel-iommu/version
     27Date:		June 2014
     28KernelVersion:	3.17
     29Contact:	Alex Williamson <alex.williamson@redhat.com>
     30Description:
     31		The architecture version as reported from the
     32		VT-d VER_REG.  Format: %d:%d, major:minor