cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sysfs-class-ocxl (1790B)


      1What:		/sys/class/ocxl/<afu name>/afu_version
      2Date:		January 2018
      3Contact:	linuxppc-dev@lists.ozlabs.org
      4Description:	read only
      5		Version of the AFU, in the format <major>:<minor>
      6		Reflects what is read in the configuration space of the AFU
      7
      8What:		/sys/class/ocxl/<afu name>/contexts
      9Date:		January 2018
     10Contact:	linuxppc-dev@lists.ozlabs.org
     11Description:	read only
     12		Number of contexts for the AFU, in the format <n>/<max>
     13		where:
     14
     15			====	===============================================
     16			n	number of currently active contexts, for debug
     17			max	maximum number of contexts supported by the AFU
     18			====	===============================================
     19
     20What:		/sys/class/ocxl/<afu name>/pp_mmio_size
     21Date:		January 2018
     22Contact:	linuxppc-dev@lists.ozlabs.org
     23Description:	read only
     24		Size of the per-process mmio area, as defined in the
     25		configuration space of the AFU
     26
     27What:		/sys/class/ocxl/<afu name>/global_mmio_size
     28Date:		January 2018
     29Contact:	linuxppc-dev@lists.ozlabs.org
     30Description:	read only
     31		Size of the global mmio area, as defined in the
     32		configuration space of the AFU
     33
     34What:		/sys/class/ocxl/<afu name>/global_mmio_area
     35Date:		January 2018
     36Contact:	linuxppc-dev@lists.ozlabs.org
     37Description:	read/write
     38		Give access the global mmio area for the AFU
     39
     40What:		/sys/class/ocxl/<afu name>/reload_on_reset
     41Date:		February 2020
     42Contact:	linuxppc-dev@lists.ozlabs.org
     43Description:	read/write
     44		Control whether the FPGA is reloaded on a link reset. Enabled
     45		through a vendor-specific logic block on the FPGA.
     46
     47			===========  ===========================================
     48			0	     Do not reload FPGA image from flash
     49			1	     Reload FPGA image from flash
     50			unavailable  The device does not support this capability
     51			===========  ===========================================