cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

arm_dsu_pmu.rst (1235B)


      1==================================
      2ARM DynamIQ Shared Unit (DSU) PMU
      3==================================
      4
      5ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
      6control logic and external interfaces to form a multicore cluster. The PMU
      7allows counting the various events related to the L3 cache, Snoop Control Unit
      8etc, using 32bit independent counters. It also provides a 64bit cycle counter.
      9
     10The PMU can only be accessed via CPU system registers and are common to the
     11cores connected to the same DSU. Like most of the other uncore PMUs, DSU
     12PMU doesn't support process specific events and cannot be used in sampling mode.
     13
     14The DSU provides a bitmap for a subset of implemented events via hardware
     15registers. There is no way for the driver to determine if the other events
     16are available or not. Hence the driver exposes only those events advertised
     17by the DSU, in "events" directory under::
     18
     19  /sys/bus/event_sources/devices/arm_dsu_<N>/
     20
     21The user should refer to the TRM of the product to figure out the supported events
     22and use the raw event code for the unlisted events.
     23
     24The driver also exposes the CPUs connected to the DSU instance in "associated_cpus".
     25
     26
     27e.g usage::
     28
     29	perf stat -a -e arm_dsu_0/cycles/