cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom_l3_pmu.rst (1419B)


      1===========================================================================
      2Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
      3===========================================================================
      4
      5This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
      6Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
      7by all cores within a socket. Each slice is exposed as a separate uncore perf
      8PMU with device name l3cache_<socket>_<instance>. User space is responsible
      9for aggregating across slices.
     10
     11The driver provides a description of its available events and configuration
     12options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
     13the driver also exposes a "cpumask" sysfs attribute which contains a mask
     14consisting of one CPU per socket which will be used to handle all the PMU
     15events on that socket.
     16
     17The hardware implements 32bit event counters and has a flat 8bit event space
     18exposed via the "event" format attribute. In addition to the 32bit physical
     19counters the driver supports virtual 64bit hardware counters by using hardware
     20counter chaining. This feature is exposed via the "lc" (long counter) format
     21flag. E.g.::
     22
     23  perf stat -e l3cache_0_0/read-miss,lc/
     24
     25Given that these are uncore PMUs the driver does not support sampling, therefore
     26"perf record" will not work. Per-task perf sessions are not supported.