cpufreq.rst (2234B)
1======================= 2S3C24XX CPUfreq support 3======================= 4 5Introduction 6------------ 7 8 The S3C24XX series support a number of power saving systems, such as 9 the ability to change the core, memory and peripheral operating 10 frequencies. The core control is exported via the CPUFreq driver 11 which has a number of different manual or automatic controls over the 12 rate the core is running at. 13 14 There are two forms of the driver depending on the specific CPU and 15 how the clocks are arranged. The first implementation used as single 16 PLL to feed the ARM, memory and peripherals via a series of dividers 17 and muxes and this is the implementation that is documented here. A 18 newer version where there is a separate PLL and clock divider for the 19 ARM core is available as a separate driver. 20 21 22Layout 23------ 24 25 The code core manages the CPU specific drivers, any data that they 26 need to register and the interface to the generic drivers/cpufreq 27 system. Each CPU registers a driver to control the PLL, clock dividers 28 and anything else associated with it. Any board that wants to use this 29 framework needs to supply at least basic details of what is required. 30 31 The core registers with drivers/cpufreq at init time if all the data 32 necessary has been supplied. 33 34 35CPU support 36----------- 37 38 The support for each CPU depends on the facilities provided by the 39 SoC and the driver as each device has different PLL and clock chains 40 associated with it. 41 42 43Slow Mode 44--------- 45 46 The SLOW mode where the PLL is turned off altogether and the 47 system is fed by the external crystal input is currently not 48 supported. 49 50 51sysfs 52----- 53 54 The core code exports extra information via sysfs in the directory 55 devices/system/cpu/cpu0/arch-freq. 56 57 58Board Support 59------------- 60 61 Each board that wants to use the cpufreq code must register some basic 62 information with the core driver to provide information about what the 63 board requires and any restrictions being placed on it. 64 65 The board needs to supply information about whether it needs the IO bank 66 timings changing, any maximum frequency limits and information about the 67 SDRAM refresh rate. 68 69 70 71 72Document Author 73--------------- 74 75Ben Dooks, Copyright 2009 Simtec Electronics 76Licensed under GPLv2