elf_hwcaps.rst (7924B)
1.. _elf_hwcaps_index: 2 3================ 4ARM64 ELF hwcaps 5================ 6 7This document describes the usage and semantics of the arm64 ELF hwcaps. 8 9 101. Introduction 11--------------- 12 13Some hardware or software features are only available on some CPU 14implementations, and/or with certain kernel configurations, but have no 15architected discovery mechanism available to userspace code at EL0. The 16kernel exposes the presence of these features to userspace through a set 17of flags called hwcaps, exposed in the auxilliary vector. 18 19Userspace software can test for features by acquiring the AT_HWCAP or 20AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant 21flags are set, e.g.:: 22 23 bool floating_point_is_present(void) 24 { 25 unsigned long hwcaps = getauxval(AT_HWCAP); 26 if (hwcaps & HWCAP_FP) 27 return true; 28 29 return false; 30 } 31 32Where software relies on a feature described by a hwcap, it should check 33the relevant hwcap flag to verify that the feature is present before 34attempting to make use of the feature. 35 36Features cannot be probed reliably through other means. When a feature 37is not available, attempting to use it may result in unpredictable 38behaviour, and is not guaranteed to result in any reliable indication 39that the feature is unavailable, such as a SIGILL. 40 41 422. Interpretation of hwcaps 43--------------------------- 44 45The majority of hwcaps are intended to indicate the presence of features 46which are described by architected ID registers inaccessible to 47userspace code at EL0. These hwcaps are defined in terms of ID register 48fields, and should be interpreted with reference to the definition of 49these fields in the ARM Architecture Reference Manual (ARM ARM). 50 51Such hwcaps are described below in the form:: 52 53 Functionality implied by idreg.field == val. 54 55Such hwcaps indicate the availability of functionality that the ARM ARM 56defines as being present when idreg.field has value val, but do not 57indicate that idreg.field is precisely equal to val, nor do they 58indicate the absence of functionality implied by other values of 59idreg.field. 60 61Other hwcaps may indicate the presence of features which cannot be 62described by ID registers alone. These may be described without 63reference to ID registers, and may refer to other documentation. 64 65 663. The hwcaps exposed in AT_HWCAP 67--------------------------------- 68 69HWCAP_FP 70 Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000. 71 72HWCAP_ASIMD 73 Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000. 74 75HWCAP_EVTSTRM 76 The generic timer is configured to generate events at a frequency of 77 approximately 10KHz. 78 79HWCAP_AES 80 Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001. 81 82HWCAP_PMULL 83 Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010. 84 85HWCAP_SHA1 86 Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001. 87 88HWCAP_SHA2 89 Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001. 90 91HWCAP_CRC32 92 Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001. 93 94HWCAP_ATOMICS 95 Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010. 96 97HWCAP_FPHP 98 Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001. 99 100HWCAP_ASIMDHP 101 Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001. 102 103HWCAP_CPUID 104 EL0 access to certain ID registers is available, to the extent 105 described by Documentation/arm64/cpu-feature-registers.rst. 106 107 These ID registers may imply the availability of features. 108 109HWCAP_ASIMDRDM 110 Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001. 111 112HWCAP_JSCVT 113 Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001. 114 115HWCAP_FCMA 116 Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001. 117 118HWCAP_LRCPC 119 Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001. 120 121HWCAP_DCPOP 122 Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001. 123 124HWCAP_SHA3 125 Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001. 126 127HWCAP_SM3 128 Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001. 129 130HWCAP_SM4 131 Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001. 132 133HWCAP_ASIMDDP 134 Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001. 135 136HWCAP_SHA512 137 Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010. 138 139HWCAP_SVE 140 Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001. 141 142HWCAP_ASIMDFHM 143 Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001. 144 145HWCAP_DIT 146 Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001. 147 148HWCAP_USCAT 149 Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001. 150 151HWCAP_ILRCPC 152 Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010. 153 154HWCAP_FLAGM 155 Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001. 156 157HWCAP_SSBS 158 Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010. 159 160HWCAP_SB 161 Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001. 162 163HWCAP_PACA 164 Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or 165 ID_AA64ISAR1_EL1.API == 0b0001, as described by 166 Documentation/arm64/pointer-authentication.rst. 167 168HWCAP_PACG 169 Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or 170 ID_AA64ISAR1_EL1.GPI == 0b0001, as described by 171 Documentation/arm64/pointer-authentication.rst. 172 173HWCAP2_DCPODP 174 175 Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. 176 177HWCAP2_SVE2 178 179 Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. 180 181HWCAP2_SVEAES 182 183 Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. 184 185HWCAP2_SVEPMULL 186 187 Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. 188 189HWCAP2_SVEBITPERM 190 191 Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. 192 193HWCAP2_SVESHA3 194 195 Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. 196 197HWCAP2_SVESM4 198 199 Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. 200 201HWCAP2_FLAGM2 202 203 Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010. 204 205HWCAP2_FRINT 206 207 Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001. 208 209HWCAP2_SVEI8MM 210 211 Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001. 212 213HWCAP2_SVEF32MM 214 215 Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001. 216 217HWCAP2_SVEF64MM 218 219 Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001. 220 221HWCAP2_SVEBF16 222 223 Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001. 224 225HWCAP2_I8MM 226 227 Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001. 228 229HWCAP2_BF16 230 231 Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001. 232 233HWCAP2_DGH 234 235 Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001. 236 237HWCAP2_RNG 238 239 Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001. 240 241HWCAP2_BTI 242 243 Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001. 244 245HWCAP2_MTE 246 247 Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described 248 by Documentation/arm64/memory-tagging-extension.rst. 249 250HWCAP2_ECV 251 252 Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. 253 254HWCAP2_AFP 255 256 Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. 257 258HWCAP2_RPRES 259 260 Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001. 261 262HWCAP2_MTE3 263 264 Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described 265 by Documentation/arm64/memory-tagging-extension.rst. 266 267HWCAP2_SME 268 269 Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described 270 by Documentation/arm64/sme.rst. 271 272HWCAP2_SME_I16I64 273 274 Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111. 275 276HWCAP2_SME_F64F64 277 278 Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1. 279 280HWCAP2_SME_I8I32 281 282 Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111. 283 284HWCAP2_SME_F16F32 285 286 Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1. 287 288HWCAP2_SME_B16F32 289 290 Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1. 291 292HWCAP2_SME_F32F32 293 294 Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1. 295 296HWCAP2_SME_FA64 297 298 Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1. 299 300HWCAP2_WFXT 301 302 Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010. 303 3044. Unused AT_HWCAP bits 305----------------------- 306 307For interoperation with userspace, the kernel guarantees that bits 62 308and 63 of AT_HWCAP will always be returned as 0.