cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hugetlbpage.rst (1468B)


      1.. _hugetlbpage_index:
      2
      3====================
      4HugeTLBpage on ARM64
      5====================
      6
      7Hugepage relies on making efficient use of TLBs to improve performance of
      8address translations. The benefit depends on both -
      9
     10  - the size of hugepages
     11  - size of entries supported by the TLBs
     12
     13The ARM64 port supports two flavours of hugepages.
     14
     151) Block mappings at the pud/pmd level
     16--------------------------------------
     17
     18These are regular hugepages where a pmd or a pud page table entry points to a
     19block of memory. Regardless of the supported size of entries in TLB, block
     20mappings reduce the depth of page table walk needed to translate hugepage
     21addresses.
     22
     232) Using the Contiguous bit
     24---------------------------
     25
     26The architecture provides a contiguous bit in the translation table entries
     27(D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
     28contiguous set of entries that can be cached in a single TLB entry.
     29
     30The contiguous bit is used in Linux to increase the mapping size at the pmd and
     31pte (last) level. The number of supported contiguous entries varies by page size
     32and level of the page table.
     33
     34
     35The following hugepage sizes are supported -
     36
     37  ====== ========   ====    ========    ===
     38  -      CONT PTE    PMD    CONT PMD    PUD
     39  ====== ========   ====    ========    ===
     40  4K:         64K     2M         32M     1G
     41  16K:         2M    32M          1G
     42  64K:         2M   512M         16G
     43  ====== ========   ====    ========    ===