sve.rst (22802B)
1=================================================== 2Scalable Vector Extension support for AArch64 Linux 3=================================================== 4 5Author: Dave Martin <Dave.Martin@arm.com> 6 7Date: 4 August 2017 8 9This document outlines briefly the interface provided to userspace by Linux in 10order to support use of the ARM Scalable Vector Extension (SVE), including 11interactions with Streaming SVE mode added by the Scalable Matrix Extension 12(SME). 13 14This is an outline of the most important features and issues only and not 15intended to be exhaustive. 16 17This document does not aim to describe the SVE architecture or programmer's 18model. To aid understanding, a minimal description of relevant programmer's 19model features for SVE is included in Appendix A. 20 21 221. General 23----------- 24 25* SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are 26 tracked per-thread. 27 28* In streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present 29 in the system, when it is not supported and these interfaces are used to 30 access streaming mode FFR is read and written as zero. 31 32* The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector 33 AT_HWCAP entry. Presence of this flag implies the presence of the SVE 34 instructions and registers, and the Linux-specific system interfaces 35 described in this document. SVE is reported in /proc/cpuinfo as "sve". 36 37* Support for the execution of SVE instructions in userspace can also be 38 detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS 39 instruction, and checking that the value of the SVE field is nonzero. [3] 40 41 It does not guarantee the presence of the system interfaces described in the 42 following sections: software that needs to verify that those interfaces are 43 present must check for HWCAP_SVE instead. 44 45* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also 46 be reported in the AT_HWCAP2 aux vector entry. In addition to this, 47 optional extensions to SVE2 may be reported by the presence of: 48 49 HWCAP2_SVE2 50 HWCAP2_SVEAES 51 HWCAP2_SVEPMULL 52 HWCAP2_SVEBITPERM 53 HWCAP2_SVESHA3 54 HWCAP2_SVESM4 55 56 This list may be extended over time as the SVE architecture evolves. 57 58 These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1, 59 which userspace can read using an MRS instruction. See elf_hwcaps.txt and 60 cpu-feature-registers.txt for details. 61 62* On hardware that supports the SME extensions, HWCAP2_SME will also be 63 reported in the AT_HWCAP2 aux vector entry. Among other things SME adds 64 streaming mode which provides a subset of the SVE feature set using a 65 separate SME vector length and the same Z/V registers. See sme.rst 66 for more details. 67 68* Debuggers should restrict themselves to interacting with the target via the 69 NT_ARM_SVE regset. The recommended way of detecting support for this regset 70 is to connect to a target process first and then attempt a 71 ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov). Note that when SME is 72 present and streaming SVE mode is in use the FPSIMD subset of registers 73 will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode 74 in the target. 75 76* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory 77 between userspace and the kernel, the register value is encoded in memory in 78 an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at 79 byte offset i from the start of the memory representation. This affects for 80 example the signal frame (struct sve_context) and ptrace interface 81 (struct user_sve_header) and associated data. 82 83 Beware that on big-endian systems this results in a different byte order than 84 for the FPSIMD V-registers, which are stored as single host-endian 128-bit 85 values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at 86 byte offset i. (struct fpsimd_context, struct user_fpsimd_state). 87 88 892. Vector length terminology 90----------------------------- 91 92The size of an SVE vector (Z) register is referred to as the "vector length". 93 94To avoid confusion about the units used to express vector length, the kernel 95adopts the following conventions: 96 97* Vector length (VL) = size of a Z-register in bytes 98 99* Vector quadwords (VQ) = size of a Z-register in units of 128 bits 100 101(So, VL = 16 * VQ.) 102 103The VQ convention is used where the underlying granularity is important, such 104as in data structure definitions. In most other situations, the VL convention 105is used. This is consistent with the meaning of the "VL" pseudo-register in 106the SVE instruction set architecture. 107 108 1093. System call behaviour 110------------------------- 111 112* On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] of 113 Z0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFR 114 become unspecified on return from a syscall. 115 116* The SVE registers are not used to pass arguments to or receive results from 117 any syscall. 118 119* In practice the affected registers/bits will be preserved or will be replaced 120 with zeros on return from a syscall, but userspace should not make 121 assumptions about this. The kernel behaviour may vary on a case-by-case 122 basis. 123 124* All other SVE state of a thread, including the currently configured vector 125 length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector 126 length (if any), is preserved across all syscalls, subject to the specific 127 exceptions for execve() described in section 6. 128 129 In particular, on return from a fork() or clone(), the parent and new child 130 process or thread share identical SVE configuration, matching that of the 131 parent before the call. 132 133 1344. Signal handling 135------------------- 136 137* A new signal frame record sve_context encodes the SVE registers on signal 138 delivery. [1] 139 140* This record is supplementary to fpsimd_context. The FPSR and FPCR registers 141 are only present in fpsimd_context. For convenience, the content of V0..V31 142 is duplicated between sve_context and fpsimd_context. 143 144* The record contains a flag field which includes a flag SVE_SIG_FLAG_SM which 145 if set indicates that the thread is in streaming mode and the vector length 146 and register data (if present) describe the streaming SVE data and vector 147 length. 148 149* The signal frame record for SVE always contains basic metadata, in particular 150 the thread's vector length (in sve_context.vl). 151 152* The SVE registers may or may not be included in the record, depending on 153 whether the registers are live for the thread. The registers are present if 154 and only if: 155 sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)). 156 157* If the registers are present, the remainder of the record has a vl-dependent 158 size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to 159 the members. 160 161* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant 162 layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the 163 start of the register's representation in memory. 164 165* If the SVE context is too big to fit in sigcontext.__reserved[], then extra 166 space is allocated on the stack, an extra_context record is written in 167 __reserved[] referencing this space. sve_context is then written in the 168 extra space. Refer to [1] for further details about this mechanism. 169 170 1715. Signal return 172----------------- 173 174When returning from a signal handler: 175 176* If there is no sve_context record in the signal frame, or if the record is 177 present but contains no register data as desribed in the previous section, 178 then the SVE registers/bits become non-live and take unspecified values. 179 180* If sve_context is present in the signal frame and contains full register 181 data, the SVE registers become live and are populated with the specified 182 data. However, for backward compatibility reasons, bits [127:0] of Z0..Z31 183 are always restored from the corresponding members of fpsimd_context.vregs[] 184 and not from sve_context. The remaining bits are restored from sve_context. 185 186* Inclusion of fpsimd_context in the signal frame remains mandatory, 187 irrespective of whether sve_context is present or not. 188 189* The vector length cannot be changed via signal return. If sve_context.vl in 190 the signal frame does not match the current vector length, the signal return 191 attempt is treated as illegal, resulting in a forced SIGSEGV. 192 193* It is permitted to enter or leave streaming mode by setting or clearing 194 the SVE_SIG_FLAG_SM flag but applications should take care to ensure that 195 when doing so sve_context.vl and any register data are appropriate for the 196 vector length in the new mode. 197 198 1996. prctl extensions 200-------------------- 201 202Some new prctl() calls are added to allow programs to manage the SVE vector 203length: 204 205prctl(PR_SVE_SET_VL, unsigned long arg) 206 207 Sets the vector length of the calling thread and related flags, where 208 arg == vl | flags. Other threads of the calling process are unaffected. 209 210 vl is the desired vector length, where sve_vl_valid(vl) must be true. 211 212 flags: 213 214 PR_SVE_VL_INHERIT 215 216 Inherit the current vector length across execve(). Otherwise, the 217 vector length is reset to the system default at execve(). (See 218 Section 9.) 219 220 PR_SVE_SET_VL_ONEXEC 221 222 Defer the requested vector length change until the next execve() 223 performed by this thread. 224 225 The effect is equivalent to implicit exceution of the following 226 call immediately after the next execve() (if any) by the thread: 227 228 prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC) 229 230 This allows launching of a new program with a different vector 231 length, while avoiding runtime side effects in the caller. 232 233 234 Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect 235 immediately. 236 237 238 Return value: a nonnegative on success, or a negative value on error: 239 EINVAL: SVE not supported, invalid vector length requested, or 240 invalid flags. 241 242 243 On success: 244 245 * Either the calling thread's vector length or the deferred vector length 246 to be applied at the next execve() by the thread (dependent on whether 247 PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value 248 supported by the system that is less than or equal to vl. If vl == 249 SVE_VL_MAX, the value set will be the largest value supported by the 250 system. 251 252 * Any previously outstanding deferred vector length change in the calling 253 thread is cancelled. 254 255 * The returned value describes the resulting configuration, encoded as for 256 PR_SVE_GET_VL. The vector length reported in this value is the new 257 current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not 258 present in arg; otherwise, the reported vector length is the deferred 259 vector length that will be applied at the next execve() by the calling 260 thread. 261 262 * Changing the vector length causes all of P0..P15, FFR and all bits of 263 Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become 264 unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current 265 vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC 266 flag, does not constitute a change to the vector length for this purpose. 267 268 269prctl(PR_SVE_GET_VL) 270 271 Gets the vector length of the calling thread. 272 273 The following flag may be OR-ed into the result: 274 275 PR_SVE_VL_INHERIT 276 277 Vector length will be inherited across execve(). 278 279 There is no way to determine whether there is an outstanding deferred 280 vector length change (which would only normally be the case between a 281 fork() or vfork() and the corresponding execve() in typical use). 282 283 To extract the vector length from the result, bitwise and it with 284 PR_SVE_VL_LEN_MASK. 285 286 Return value: a nonnegative value on success, or a negative value on error: 287 EINVAL: SVE not supported. 288 289 2907. ptrace extensions 291--------------------- 292 293* New regsets NT_ARM_SVE and NT_ARM_SSVE are defined for use with 294 PTRACE_GETREGSET and PTRACE_SETREGSET. NT_ARM_SSVE describes the 295 streaming mode SVE registers and NT_ARM_SVE describes the 296 non-streaming mode SVE registers. 297 298 In this description a register set is referred to as being "live" when 299 the target is in the appropriate streaming or non-streaming mode and is 300 using data beyond the subset shared with the FPSIMD Vn registers. 301 302 Refer to [2] for definitions. 303 304The regset data starts with struct user_sve_header, containing: 305 306 size 307 308 Size of the complete regset, in bytes. 309 This depends on vl and possibly on other things in the future. 310 311 If a call to PTRACE_GETREGSET requests less data than the value of 312 size, the caller can allocate a larger buffer and retry in order to 313 read the complete regset. 314 315 max_size 316 317 Maximum size in bytes that the regset can grow to for the target 318 thread. The regset won't grow bigger than this even if the target 319 thread changes its vector length etc. 320 321 vl 322 323 Target thread's current vector length, in bytes. 324 325 max_vl 326 327 Maximum possible vector length for the target thread. 328 329 flags 330 331 at most one of 332 333 SVE_PT_REGS_FPSIMD 334 335 SVE registers are not live (GETREGSET) or are to be made 336 non-live (SETREGSET). 337 338 The payload is of type struct user_fpsimd_state, with the same 339 meaning as for NT_PRFPREG, starting at offset 340 SVE_PT_FPSIMD_OFFSET from the start of user_sve_header. 341 342 Extra data might be appended in the future: the size of the 343 payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags). 344 345 vq should be obtained using sve_vq_from_vl(vl). 346 347 or 348 349 SVE_PT_REGS_SVE 350 351 SVE registers are live (GETREGSET) or are to be made live 352 (SETREGSET). 353 354 The payload contains the SVE register data, starting at offset 355 SVE_PT_SVE_OFFSET from the start of user_sve_header, and with 356 size SVE_PT_SVE_SIZE(vq, flags); 357 358 ... OR-ed with zero or more of the following flags, which have the same 359 meaning and behaviour as the corresponding PR_SET_VL_* flags: 360 361 SVE_PT_VL_INHERIT 362 363 SVE_PT_VL_ONEXEC (SETREGSET only). 364 365 If neither FPSIMD nor SVE flags are provided then no register 366 payload is available, this is only possible when SME is implemented. 367 368 369* The effects of changing the vector length and/or flags are equivalent to 370 those documented for PR_SVE_SET_VL. 371 372 The caller must make a further GETREGSET call if it needs to know what VL is 373 actually set by SETREGSET, unless is it known in advance that the requested 374 VL is supported. 375 376* In the SVE_PT_REGS_SVE case, the size and layout of the payload depends on 377 the header fields. The SVE_PT_SVE_*() macros are provided to facilitate 378 access to the members. 379 380* In either case, for SETREGSET it is permissible to omit the payload, in which 381 case only the vector length and flags are changed (along with any 382 consequences of those changes). 383 384* In systems supporting SME when in streaming mode a GETREGSET for 385 NT_REG_SVE will return only the user_sve_header with no register data, 386 similarly a GETREGSET for NT_REG_SSVE will not return any register data 387 when not in streaming mode. 388 389* A GETREGSET for NT_ARM_SSVE will never return SVE_PT_REGS_FPSIMD. 390 391* For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the 392 requested VL is not supported, the effect will be the same as if the 393 payload were omitted, except that an EIO error is reported. No 394 attempt is made to translate the payload data to the correct layout 395 for the vector length actually set. The thread's FPSIMD state is 396 preserved, but the remaining bits of the SVE registers become 397 unspecified. It is up to the caller to translate the payload layout 398 for the actual VL and retry. 399 400* Where SME is implemented it is not possible to GETREGSET the register 401 state for normal SVE when in streaming mode, nor the streaming mode 402 register state when in normal mode, regardless of the implementation defined 403 behaviour of the hardware for sharing data between the two modes. 404 405* Any SETREGSET of NT_ARM_SVE will exit streaming mode if the target was in 406 streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode 407 if the target was not in streaming mode. 408 409* The effect of writing a partial, incomplete payload is unspecified. 410 411 4128. ELF coredump extensions 413--------------------------- 414 415* NT_ARM_SVE and NT_ARM_SSVE notes will be added to each coredump for 416 each thread of the dumped process. The contents will be equivalent to the 417 data that would have been read if a PTRACE_GETREGSET of the corresponding 418 type were executed for each thread when the coredump was generated. 419 4209. System runtime configuration 421-------------------------------- 422 423* To mitigate the ABI impact of expansion of the signal frame, a policy 424 mechanism is provided for administrators, distro maintainers and developers 425 to set the default vector length for userspace processes: 426 427/proc/sys/abi/sve_default_vector_length 428 429 Writing the text representation of an integer to this file sets the system 430 default vector length to the specified value, unless the value is greater 431 than the maximum vector length supported by the system in which case the 432 default vector length is set to that maximum. 433 434 The result can be determined by reopening the file and reading its 435 contents. 436 437 At boot, the default vector length is initially set to 64 or the maximum 438 supported vector length, whichever is smaller. This determines the initial 439 vector length of the init process (PID 1). 440 441 Reading this file returns the current system default vector length. 442 443* At every execve() call, the new vector length of the new process is set to 444 the system default vector length, unless 445 446 * PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the 447 calling thread, or 448 449 * a deferred vector length change is pending, established via the 450 PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC). 451 452* Modifying the system default vector length does not affect the vector length 453 of any existing process or thread that does not make an execve() call. 454 455 456Appendix A. SVE programmer's model (informative) 457================================================= 458 459This section provides a minimal description of the additions made by SVE to the 460ARMv8-A programmer's model that are relevant to this document. 461 462Note: This section is for information only and not intended to be complete or 463to replace any architectural specification. 464 465A.1. Registers 466--------------- 467 468In A64 state, SVE adds the following: 469 470* 32 8VL-bit vector registers Z0..Z31 471 For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn. 472 473 A register write using a Vn register name zeros all bits of the corresponding 474 Zn except for bits [127:0]. 475 476* 16 VL-bit predicate registers P0..P15 477 478* 1 VL-bit special-purpose predicate register FFR (the "first-fault register") 479 480* a VL "pseudo-register" that determines the size of each vector register 481 482 The SVE instruction set architecture provides no way to write VL directly. 483 Instead, it can be modified only by EL1 and above, by writing appropriate 484 system registers. 485 486* The value of VL can be configured at runtime by EL1 and above: 487 16 <= VL <= VLmax, where VL must be a multiple of 16. 488 489* The maximum vector length is determined by the hardware: 490 16 <= VLmax <= 256. 491 492 (The SVE architecture specifies 256, but permits future architecture 493 revisions to raise this limit.) 494 495* FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point 496 operations in a similar way to the way in which they interact with ARMv8 497 floating-point operations:: 498 499 8VL-1 128 0 bit index 500 +---- //// -----------------+ 501 Z0 | : V0 | 502 : : 503 Z7 | : V7 | 504 Z8 | : * V8 | 505 : : : 506 Z15 | : *V15 | 507 Z16 | : V16 | 508 : : 509 Z31 | : V31 | 510 +---- //// -----------------+ 511 31 0 512 VL-1 0 +-------+ 513 +---- //// --+ FPSR | | 514 P0 | | +-------+ 515 : | | *FPCR | | 516 P15 | | +-------+ 517 +---- //// --+ 518 FFR | | +-----+ 519 +---- //// --+ VL | | 520 +-----+ 521 522(*) callee-save: 523 This only applies to bits [63:0] of Z-/V-registers. 524 FPCR contains callee-save and caller-save bits. See [4] for details. 525 526 527A.2. Procedure call standard 528----------------------------- 529 530The ARMv8-A base procedure call standard is extended as follows with respect to 531the additional SVE register state: 532 533* All SVE register bits that are not shared with FP/SIMD are caller-save. 534 535* Z8 bits [63:0] .. Z15 bits [63:0] are callee-save. 536 537 This follows from the way these bits are mapped to V8..V15, which are caller- 538 save in the base procedure call standard. 539 540 541Appendix B. ARMv8-A FP/SIMD programmer's model 542=============================================== 543 544Note: This section is for information only and not intended to be complete or 545to replace any architectural specification. 546 547Refer to [4] for more information. 548 549ARMv8-A defines the following floating-point / SIMD register state: 550 551* 32 128-bit vector registers V0..V31 552* 2 32-bit status/control registers FPSR, FPCR 553 554:: 555 556 127 0 bit index 557 +---------------+ 558 V0 | | 559 : : : 560 V7 | | 561 * V8 | | 562 : : : : 563 *V15 | | 564 V16 | | 565 : : : 566 V31 | | 567 +---------------+ 568 569 31 0 570 +-------+ 571 FPSR | | 572 +-------+ 573 *FPCR | | 574 +-------+ 575 576(*) callee-save: 577 This only applies to bits [63:0] of V-registers. 578 FPCR contains a mixture of callee-save and caller-save bits. 579 580 581References 582========== 583 584[1] arch/arm64/include/uapi/asm/sigcontext.h 585 AArch64 Linux signal ABI definitions 586 587[2] arch/arm64/include/uapi/asm/ptrace.h 588 AArch64 Linux ptrace ABI definitions 589 590[3] Documentation/arm64/cpu-feature-registers.rst 591 592[4] ARM IHI0055C 593 http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf 594 http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html 595 Procedure Call Standard for the ARM 64-bit Architecture (AArch64)