cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,berlin-smp (1027B)

      1========================================================
      2Secondary CPU enable-method "marvell,berlin-smp" binding
      3========================================================
      4
      5This document describes the "marvell,berlin-smp" method for enabling secondary
      6CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
      7be defined in the "cpus" node.
      8
      9Enable method name:	"marvell,berlin-smp"
     10Compatible machines:	"marvell,berlin2" and "marvell,berlin2q"
     11Compatible CPUs:	"marvell,pj4b" and "arm,cortex-a9"
     12Related properties:	(none)
     13
     14Note:
     15This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
     16"marvell,berlin-cpu-ctrl"[1].
     17
     18Example:
     19
     20	cpus {
     21		#address-cells = <1>;
     22		#size-cells = <0>;
     23		enable-method = "marvell,berlin-smp";
     24
     25		cpu@0 {
     26			compatible = "marvell,pj4b";
     27			device_type = "cpu";
     28			next-level-cache = <&l2>;
     29			reg = <0>;
     30		};
     31
     32		cpu@1 {
     33			compatible = "marvell,pj4b";
     34			device_type = "cpu";
     35			next-level-cache = <&l2>;
     36			reg = <1>;
     37		};
     38	};
     39
     40--
     41[1] arm/marvell,berlin.txt