ete.yaml (2112B)
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2# Copyright 2021, Arm Ltd 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/arm/ete.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: ARM Embedded Trace Extensions 9 10maintainers: 11 - Suzuki K Poulose <suzuki.poulose@arm.com> 12 - Mathieu Poirier <mathieu.poirier@linaro.org> 13 14description: | 15 Arm Embedded Trace Extension(ETE) is a per CPU trace component that 16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 17 architecture and has extended support for future architecture changes. 18 The trace generated by the ETE could be stored via legacy CoreSight 19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer 20 Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to 21 legacy CoreSight components, a node must be listed per instance, along 22 with any optional connection graph as per the coresight bindings. 23 See bindings/arm/coresight.txt. 24 25properties: 26 $nodename: 27 pattern: "^ete([0-9a-f]+)$" 28 compatible: 29 items: 30 - const: arm,embedded-trace-extension 31 32 cpu: 33 description: | 34 Handle to the cpu this ETE is bound to. 35 $ref: /schemas/types.yaml#/definitions/phandle 36 37 out-ports: 38 description: | 39 Output connections from the ETE to legacy CoreSight trace bus. 40 $ref: /schemas/graph.yaml#/properties/ports 41 properties: 42 port: 43 description: Output connection from the ETE to legacy CoreSight Trace bus. 44 $ref: /schemas/graph.yaml#/properties/port 45 46required: 47 - compatible 48 - cpu 49 50additionalProperties: false 51 52examples: 53 54# An ETE node without legacy CoreSight connections 55 - | 56 ete0 { 57 compatible = "arm,embedded-trace-extension"; 58 cpu = <&cpu_0>; 59 }; 60# An ETE node with legacy CoreSight connections 61 - | 62 ete1 { 63 compatible = "arm,embedded-trace-extension"; 64 cpu = <&cpu_1>; 65 66 out-ports { /* legacy coresight connection */ 67 port { 68 ete1_out_port: endpoint { 69 remote-endpoint = <&funnel_in_port0>; 70 }; 71 }; 72 }; 73 }; 74 75...