cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx7ulp-sim.yaml (939B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale i.MX7ULP System Integration Module
      8
      9maintainers:
     10  - Anson Huang <anson.huang@nxp.com>
     11
     12description: |
     13  The system integration module (SIM) provides system control and chip configuration
     14  registers. In this module, chip revision information is located in JTAG ID register,
     15  and a set of registers have been made available in DGO domain for SW use, with the
     16  objective to maintain its value between system resets.
     17
     18properties:
     19  compatible:
     20    items:
     21      - const: fsl,imx7ulp-sim
     22      - const: syscon
     23
     24  reg:
     25    maxItems: 1
     26
     27required:
     28  - compatible
     29  - reg
     30
     31additionalProperties: false
     32
     33examples:
     34  - |
     35    sim@410a3000 {
     36        compatible = "fsl,imx7ulp-sim", "syscon";
     37        reg = <0x410a3000 0x1000>;
     38    };