cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hi3798cv200-perictrl.yaml (1443B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Hisilicon Hi3798CV200 Peripheral Controller
      8
      9maintainers:
     10  - Wei Xu <xuwei5@hisilicon.com>
     11
     12description: |
     13  The Hi3798CV200 Peripheral Controller controls peripherals, queries
     14  their status, and configures some functions of peripherals.
     15
     16properties:
     17  compatible:
     18    items:
     19      - const: hisilicon,hi3798cv200-perictrl
     20      - const: syscon
     21      - const: simple-mfd
     22
     23  reg:
     24    maxItems: 1
     25
     26  "#address-cells":
     27    const: 1
     28
     29  "#size-cells":
     30    const: 1
     31
     32  ranges: true
     33
     34required:
     35  - compatible
     36  - reg
     37  - "#address-cells"
     38  - "#size-cells"
     39  - ranges
     40
     41additionalProperties:
     42  type: object
     43
     44examples:
     45  - |
     46    peripheral-controller@8a20000 {
     47        compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
     48        reg = <0x8a20000 0x1000>;
     49        #address-cells = <1>;
     50        #size-cells = <1>;
     51        ranges = <0x0 0x8a20000 0x1000>;
     52
     53        phy@850 {
     54            compatible = "hisilicon,hi3798cv200-combphy";
     55            reg = <0x850 0x8>;
     56            #phy-cells = <1>;
     57            clocks = <&crg 42>;
     58            resets = <&crg 0x188 4>;
     59            assigned-clocks = <&crg 42>;
     60            assigned-clock-rates = <100000000>;
     61            hisilicon,fixed-mode = <4>;
     62        };
     63    };
     64...