cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,k3-sci-common.yaml (1803B)

      1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Common K3 TI-SCI bindings
      8
      9maintainers:
     10  - Nishanth Menon <nm@ti.com>
     11
     12description: |
     13  The TI K3 family of SoCs usually have a central System Controller Processor
     14  that is responsible for managing various SoC-level resources like clocks,
     15  resets, interrupts etc. The communication with that processor is performed
     16  through the TI-SCI protocol.
     17
     18  Each specific device management node like a clock controller node, a reset
     19  controller node or an interrupt-controller node should define a common set
     20  of properties that enables them to implement the corresponding functionality
     21  over the TI-SCI protocol. The following are some of the common properties
     22  needed by such individual nodes. The required properties for each device
     23  management node is defined in the respective binding.
     24
     25properties:
     26  ti,sci:
     27    $ref: /schemas/types.yaml#/definitions/phandle
     28    description:
     29      Should be a phandle to the TI-SCI System Controller node
     30
     31  ti,sci-dev-id:
     32    $ref: /schemas/types.yaml#/definitions/uint32
     33    description: |
     34      Should contain the TI-SCI device id corresponding to the device. Please
     35      refer to the corresponding System Controller documentation for valid
     36      values for the desired device.
     37
     38  ti,sci-proc-ids:
     39    description: Should contain a single tuple of <proc_id host_id>.
     40    $ref: /schemas/types.yaml#/definitions/uint32-array
     41    items:
     42      - description: TI-SCI processor id for the remote processor device
     43      - description: TI-SCI host id to which processor control ownership
     44                     should be transferred to
     45
     46additionalProperties: true