cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mediatek,infracfg.yaml (2099B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: MediaTek Infrastructure System Configuration Controller
      8
      9maintainers:
     10  - Matthias Brugger <matthias.bgg@gmail.com>
     11
     12description:
     13  The Mediatek infracfg controller provides various clocks and reset outputs
     14  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
     15  and reset values in <dt-bindings/reset/mt*-reset.h> and
     16  <dt-bindings/reset/mt*-resets.h>.
     17
     18properties:
     19  compatible:
     20    oneOf:
     21      - items:
     22          - enum:
     23              - mediatek,mt2701-infracfg
     24              - mediatek,mt2712-infracfg
     25              - mediatek,mt6765-infracfg
     26              - mediatek,mt6779-infracfg_ao
     27              - mediatek,mt6797-infracfg
     28              - mediatek,mt7622-infracfg
     29              - mediatek,mt7629-infracfg
     30              - mediatek,mt7986-infracfg
     31              - mediatek,mt8135-infracfg
     32              - mediatek,mt8167-infracfg
     33              - mediatek,mt8173-infracfg
     34              - mediatek,mt8183-infracfg
     35              - mediatek,mt8516-infracfg
     36          - const: syscon
     37      - items:
     38          - const: mediatek,mt7623-infracfg
     39          - const: mediatek,mt2701-infracfg
     40          - const: syscon
     41
     42  reg:
     43    maxItems: 1
     44
     45  '#clock-cells':
     46    const: 1
     47
     48  '#reset-cells':
     49    const: 1
     50
     51required:
     52  - compatible
     53  - reg
     54  - '#clock-cells'
     55
     56if:
     57  properties:
     58    compatible:
     59      contains:
     60        enum:
     61          - mediatek,mt2701-infracfg
     62          - mediatek,mt2712-infracfg
     63          - mediatek,mt7622-infracfg
     64          - mediatek,mt7986-infracfg
     65          - mediatek,mt8135-infracfg
     66          - mediatek,mt8173-infracfg
     67          - mediatek,mt8183-infracfg
     68then:
     69  required:
     70    - '#reset-cells'
     71
     72additionalProperties: false
     73
     74examples:
     75  - |
     76    infracfg: clock-controller@10001000 {
     77        compatible = "mediatek,mt8173-infracfg", "syscon";
     78        reg = <0x10001000 0x1000>;
     79        #clock-cells = <1>;
     80        #reset-cells = <1>;
     81    };