cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

mediatek,mt8192-sys-clock.yaml (1490B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: MediaTek System Clock Controller for MT8192
      8
      9maintainers:
     10  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
     11
     12description:
     13  The Mediatek system clock controller provides various clocks and system configuration
     14  like reset and bus protection on MT8192.
     15
     16properties:
     17  compatible:
     18    items:
     19      - enum:
     20          - mediatek,mt8192-topckgen
     21          - mediatek,mt8192-infracfg
     22          - mediatek,mt8192-pericfg
     23          - mediatek,mt8192-apmixedsys
     24      - const: syscon
     25
     26  reg:
     27    maxItems: 1
     28
     29  '#clock-cells':
     30    const: 1
     31
     32required:
     33  - compatible
     34  - reg
     35
     36additionalProperties: false
     37
     38examples:
     39  - |
     40    topckgen: syscon@10000000 {
     41        compatible = "mediatek,mt8192-topckgen", "syscon";
     42        reg = <0x10000000 0x1000>;
     43        #clock-cells = <1>;
     44    };
     45
     46  - |
     47    infracfg: syscon@10001000 {
     48        compatible = "mediatek,mt8192-infracfg", "syscon";
     49        reg = <0x10001000 0x1000>;
     50        #clock-cells = <1>;
     51    };
     52
     53  - |
     54    pericfg: syscon@10003000 {
     55        compatible = "mediatek,mt8192-pericfg", "syscon";
     56        reg = <0x10003000 0x1000>;
     57        #clock-cells = <1>;
     58    };
     59
     60  - |
     61    apmixedsys: syscon@1000c000 {
     62        compatible = "mediatek,mt8192-apmixedsys", "syscon";
     63        reg = <0x1000c000 0x1000>;
     64        #clock-cells = <1>;
     65    };