cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mediatek,mt8195-sys-clock.yaml (1820B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: MediaTek System Clock Controller for MT8195
      8
      9maintainers:
     10  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
     11
     12description:
     13  The clock architecture in Mediatek like below
     14  PLLs -->
     15          dividers -->
     16                      muxes
     17                           -->
     18                              clock gate
     19
     20  The apmixedsys provides most of PLLs which generated from SoC 26m.
     21  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
     22  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
     23
     24properties:
     25  compatible:
     26    items:
     27      - enum:
     28          - mediatek,mt8195-topckgen
     29          - mediatek,mt8195-infracfg_ao
     30          - mediatek,mt8195-apmixedsys
     31          - mediatek,mt8195-pericfg_ao
     32      - const: syscon
     33
     34  reg:
     35    maxItems: 1
     36
     37  '#clock-cells':
     38    const: 1
     39
     40required:
     41  - compatible
     42  - reg
     43
     44additionalProperties: false
     45
     46examples:
     47  - |
     48    topckgen: syscon@10000000 {
     49        compatible = "mediatek,mt8195-topckgen", "syscon";
     50        reg = <0x10000000 0x1000>;
     51        #clock-cells = <1>;
     52    };
     53
     54  - |
     55    infracfg_ao: syscon@10001000 {
     56        compatible = "mediatek,mt8195-infracfg_ao", "syscon";
     57        reg = <0x10001000 0x1000>;
     58        #clock-cells = <1>;
     59    };
     60
     61  - |
     62    apmixedsys: syscon@1000c000 {
     63        compatible = "mediatek,mt8195-apmixedsys", "syscon";
     64        reg = <0x1000c000 0x1000>;
     65        #clock-cells = <1>;
     66    };
     67
     68  - |
     69    pericfg_ao: syscon@11003000 {
     70        compatible = "mediatek,mt8195-pericfg_ao", "syscon";
     71        reg = <0x11003000 0x1000>;
     72        #clock-cells = <1>;
     73    };