cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mstar,smpctrl.yaml (939B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2# Copyright 2020 thingy.jp.
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: MStar/SigmaStar Armv7 SoC SMP control registers
      9
     10maintainers:
     11  - Daniel Palmer <daniel@thingy.jp>
     12
     13description: |
     14  MStar/SigmaStar's Armv7 SoCs that have more than one processor
     15  have a region of registers that allow setting the boot address
     16  and a magic number that allows secondary processors to leave
     17  the loop they are parked in by the boot ROM.
     18
     19properties:
     20  compatible:
     21    items:
     22      - enum:
     23          - sstar,ssd201-smpctrl # SSD201/SSD202D
     24      - const: mstar,smpctrl
     25
     26  reg:
     27    maxItems: 1
     28
     29required:
     30  - compatible
     31  - reg
     32
     33additionalProperties: false
     34
     35examples:
     36  - |
     37    smpctrl@204000 {
     38        compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
     39        reg = <0x204000 0x200>;
     40    };