cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun4i-a10-mbus.yaml (3446B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner Memory Bus (MBUS) controller
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13description: |
     14  The MBUS controller drives the MBUS that other devices in the SoC
     15  will use to perform DMA. It also has a register interface that
     16  allows to monitor and control the bandwidth and priorities for
     17  masters on that bus.
     18
     19  Each device having to perform their DMA through the MBUS must have
     20  the interconnects and interconnect-names properties set to the MBUS
     21  controller and with "dma-mem" as the interconnect name.
     22
     23properties:
     24  "#interconnect-cells":
     25    const: 1
     26    description:
     27      The content of the cell is the MBUS ID.
     28
     29  compatible:
     30    enum:
     31      - allwinner,sun5i-a13-mbus
     32      - allwinner,sun8i-h3-mbus
     33      - allwinner,sun8i-r40-mbus
     34      - allwinner,sun50i-a64-mbus
     35      - allwinner,sun50i-h5-mbus
     36
     37  reg:
     38    minItems: 1
     39    items:
     40      - description: MBUS interconnect/bandwidth limit/PMU registers
     41      - description: DRAM controller/PHY registers
     42
     43  reg-names:
     44    minItems: 1
     45    items:
     46      - const: mbus
     47      - const: dram
     48
     49  clocks:
     50    minItems: 1
     51    items:
     52      - description: MBUS interconnect module clock
     53      - description: DRAM controller/PHY module clock
     54      - description: Register bus clock, shared by MBUS and DRAM
     55
     56  clock-names:
     57    minItems: 1
     58    items:
     59      - const: mbus
     60      - const: dram
     61      - const: bus
     62
     63  interrupts:
     64    maxItems: 1
     65    description:
     66      MBUS PMU activity interrupt.
     67
     68  dma-ranges:
     69    description:
     70      See section 2.3.9 of the DeviceTree Specification.
     71
     72  '#address-cells': true
     73
     74  '#size-cells': true
     75
     76required:
     77  - "#interconnect-cells"
     78  - compatible
     79  - reg
     80  - clocks
     81  - dma-ranges
     82
     83if:
     84  properties:
     85    compatible:
     86      contains:
     87        enum:
     88          - allwinner,sun8i-h3-mbus
     89          - allwinner,sun50i-a64-mbus
     90          - allwinner,sun50i-h5-mbus
     91
     92then:
     93  properties:
     94    reg:
     95      minItems: 2
     96
     97    reg-names:
     98      minItems: 2
     99
    100    clocks:
    101      minItems: 3
    102
    103    clock-names:
    104      minItems: 3
    105
    106  required:
    107    - reg-names
    108    - clock-names
    109
    110else:
    111  properties:
    112    reg:
    113      maxItems: 1
    114
    115    reg-names:
    116      maxItems: 1
    117
    118    clocks:
    119      maxItems: 1
    120
    121    clock-names:
    122      maxItems: 1
    123
    124additionalProperties: false
    125
    126examples:
    127  - |
    128    #include <dt-bindings/clock/sun50i-a64-ccu.h>
    129    #include <dt-bindings/interrupt-controller/arm-gic.h>
    130
    131    dram-controller@1c01000 {
    132        compatible = "allwinner,sun5i-a13-mbus";
    133        reg = <0x01c01000 0x1000>;
    134        clocks = <&ccu CLK_MBUS>;
    135        #address-cells = <1>;
    136        #size-cells = <1>;
    137        dma-ranges = <0x00000000 0x40000000 0x20000000>;
    138        #interconnect-cells = <1>;
    139    };
    140
    141  - |
    142    dram-controller@1c62000 {
    143        compatible = "allwinner,sun50i-a64-mbus";
    144        reg = <0x01c62000 0x1000>,
    145              <0x01c63000 0x1000>;
    146        reg-names = "mbus", "dram";
    147        clocks = <&ccu CLK_MBUS>,
    148                 <&ccu CLK_DRAM>,
    149                 <&ccu CLK_BUS_DRAM>;
    150        clock-names = "mbus", "dram", "bus";
    151        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
    152        #address-cells = <1>;
    153        #size-cells = <1>;
    154        dma-ranges = <0x00000000 0x40000000 0xc0000000>;
    155        #interconnect-cells = <1>;
    156    };
    157
    158...