cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

syna.txt (3097B)

      1Synaptics SoC Device Tree Bindings
      2
      3According to https://www.synaptics.com/company/news/conexant-marvell
      4Synaptics has acquired the Multimedia Solutions Business of Marvell, so
      5berlin SoCs are now Synaptics' SoCs now.
      6
      7---------------------------------------------------------------
      8
      9Work in progress statement:
     10
     11Device tree files and bindings applying to Marvell Berlin SoCs and boards are
     12considered "unstable". Any Marvell Berlin device tree binding may change at any
     13time. Be sure to use a device tree binary and a kernel image generated from the
     14same source tree.
     15
     16Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
     17stable binding/ABI.
     18
     19---------------------------------------------------------------
     20
     21Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
     22shall have the following properties:
     23
     24* Required root node properties:
     25compatible: must contain "marvell,berlin"
     26
     27In addition, the above compatible shall be extended with the specific
     28SoC and board used. Currently known SoC compatibles are:
     29    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
     30    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
     31    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
     32    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)
     33    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
     34
     35* Example:
     36
     37/ {
     38	model = "Sony NSZ-GS7";
     39	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
     40
     41	...
     42}
     43
     44* Marvell Berlin CPU control bindings
     45
     46CPU control register allows various operations on CPUs, like resetting them
     47independently.
     48
     49Required properties:
     50- compatible: should be "marvell,berlin-cpu-ctrl"
     51- reg: address and length of the register set
     52
     53Example:
     54
     55cpu-ctrl@f7dd0000 {
     56	compatible = "marvell,berlin-cpu-ctrl";
     57	reg = <0xf7dd0000 0x10000>;
     58};
     59
     60* Marvell Berlin2 chip control binding
     61
     62Marvell Berlin SoCs have a chip control register set providing several
     63individual registers dealing with pinmux, padmux, clock, reset, and secondary
     64CPU boot address. Unfortunately, the individual registers are spread among the
     65chip control registers, so there should be a single DT node only providing the
     66different functions which are described below.
     67
     68Required properties:
     69- compatible:
     70	* the first and second values must be:
     71		"simple-mfd", "syscon"
     72- reg: address and length of following register sets for
     73  BG2/BG2CD: chip control register set
     74  BG2Q: chip control register set and cpu pll registers
     75
     76* Marvell Berlin2 system control binding
     77
     78Marvell Berlin SoCs have a system control register set providing several
     79individual registers dealing with pinmux, padmux, and reset.
     80
     81Required properties:
     82- compatible:
     83	* the first and second values must be:
     84		"simple-mfd", "syscon"
     85- reg: address and length of the system control register set
     86
     87Example:
     88
     89chip: chip-control@ea0000 {
     90	compatible = "simple-mfd", "syscon";
     91	reg = <0xea0000 0x400>;
     92
     93	/* sub-device nodes */
     94};
     95
     96sysctrl: system-controller@d000 {
     97	compatible = "simple-mfd", "syscon";
     98	reg = <0xd000 0x100>;
     99
    100	/* sub-device nodes */
    101};