cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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trbe.yaml (1215B)

      1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
      2# Copyright 2021, Arm Ltd
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: ARM Trace Buffer Extensions
      9
     10maintainers:
     11  - Anshuman Khandual <anshuman.khandual@arm.com>
     12
     13description: |
     14  Arm Trace Buffer Extension (TRBE) is a per CPU component
     15  for storing trace generated on the CPU to memory. It is
     16  accessed via CPU system registers. The software can verify
     17  if it is permitted to use the component by checking the
     18  TRBIDR register.
     19
     20properties:
     21  $nodename:
     22    const: "trbe"
     23  compatible:
     24    items:
     25      - const: arm,trace-buffer-extension
     26
     27  interrupts:
     28    description: |
     29       Exactly 1 PPI must be listed. For heterogeneous systems where
     30       TRBE is only supported on a subset of the CPUs, please consult
     31       the arm,gic-v3 binding for details on describing a PPI partition.
     32    maxItems: 1
     33
     34required:
     35  - compatible
     36  - interrupts
     37
     38additionalProperties: false
     39
     40examples:
     41
     42  - |
     43   #include <dt-bindings/interrupt-controller/arm-gic.h>
     44
     45   trbe {
     46     compatible = "arm,trace-buffer-extension";
     47     interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
     48   };
     49...