cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ahci-fsl-qoriq.txt (768B)

      1Binding for Freescale QorIQ AHCI SATA Controller
      2
      3Required properties:
      4  - reg: Physical base address and size of the controller's register area.
      5  - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
      6    chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
      7  - clocks: Input clock specifier. Refer to common clock bindings.
      8  - interrupts: Interrupt specifier. Refer to interrupt binding.
      9
     10Optional properties:
     11  - dma-coherent: Enable AHCI coherent DMA operation.
     12  - reg-names: register area names when there are more than 1 register area.
     13
     14Examples:
     15	sata@3200000 {
     16		compatible = "fsl,ls1021a-ahci";
     17		reg = <0x0 0x3200000 0x0 0x10000>;
     18		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
     19		clocks = <&platform_clk 1>;
     20		dma-coherent;
     21	};