cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun8i-r40-ahci.yaml (1378B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner R40 AHCI SATA Controller bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  compatible:
     15    const: allwinner,sun8i-r40-ahci
     16
     17  reg:
     18    maxItems: 1
     19
     20  clocks:
     21    items:
     22      - description: AHCI Bus Clock
     23      - description: AHCI Module Clock
     24
     25  interrupts:
     26    maxItems: 1
     27
     28  resets:
     29    maxItems: 1
     30
     31  reset-names:
     32    const: ahci
     33
     34  ahci-supply:
     35    description: Regulator for the AHCI controller
     36
     37  phy-supply:
     38    description: Regulator for the SATA PHY power
     39
     40required:
     41  - compatible
     42  - reg
     43  - clocks
     44  - interrupts
     45  - resets
     46  - reset-names
     47
     48additionalProperties: false
     49
     50examples:
     51  - |
     52    #include <dt-bindings/interrupt-controller/arm-gic.h>
     53    #include <dt-bindings/clock/sun8i-r40-ccu.h>
     54    #include <dt-bindings/reset/sun8i-r40-ccu.h>
     55
     56    ahci: sata@1c18000 {
     57        compatible = "allwinner,sun8i-r40-ahci";
     58        reg = <0x01c18000 0x1000>;
     59        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
     60        clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
     61        resets = <&ccu RST_BUS_SATA>;
     62        reset-names = "ahci";
     63        ahci-supply = <&reg_dldo4>;
     64        phy-supply = <&reg_eldo3>;
     65    };
     66
     67...