cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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apm-xgene.txt (2279B)

      1* APM X-Gene 6.0 Gb/s SATA host controller nodes
      2
      3SATA host controller nodes are defined to describe on-chip Serial ATA
      4controllers. Each SATA controller (pair of ports) have its own node.
      5
      6Required properties:
      7- compatible		: Shall contain:
      8  * "apm,xgene-ahci"
      9- reg			: First memory resource shall be the AHCI memory
     10			  resource.
     11			  Second memory resource shall be the host controller
     12			  core memory resource.
     13			  Third memory resource shall be the host controller
     14			  diagnostic memory resource.
     15			  4th memory resource shall be the host controller
     16			  AXI memory resource.
     17			  5th optional memory resource shall be the host
     18			  controller MUX memory resource if required.
     19- interrupts		: Interrupt-specifier for SATA host controller IRQ.
     20- clocks		: Reference to the clock entry.
     21- phys			: A list of phandles + phy-specifiers, one for each
     22			  entry in phy-names.
     23- phy-names		: Should contain:
     24  * "sata-phy" for the SATA 6.0Gbps PHY
     25
     26Optional properties:
     27- dma-coherent		: Present if dma operations are coherent
     28- status		: Shall be "ok" if enabled or "disabled" if disabled.
     29			  Default is "ok".
     30
     31Example:
     32		sataclk: sataclk {
     33			compatible = "fixed-clock";
     34			#clock-cells = <1>;
     35			clock-frequency = <100000000>;
     36			clock-output-names = "sataclk";
     37		};
     38
     39		phy2: phy@1f22a000 {
     40			compatible = "apm,xgene-phy";
     41			reg = <0x0 0x1f22a000 0x0 0x100>;
     42			#phy-cells = <1>;
     43		};
     44
     45		phy3: phy@1f23a000 {
     46			compatible = "apm,xgene-phy";
     47			reg = <0x0 0x1f23a000 0x0 0x100>;
     48			#phy-cells = <1>;
     49		};
     50
     51		sata2: sata@1a400000 {
     52			compatible = "apm,xgene-ahci";
     53			reg = <0x0 0x1a400000 0x0 0x1000>,
     54			      <0x0 0x1f220000 0x0 0x1000>,
     55			      <0x0 0x1f22d000 0x0 0x1000>,
     56			      <0x0 0x1f22e000 0x0 0x1000>,
     57			      <0x0 0x1f227000 0x0 0x1000>;
     58			interrupts = <0x0 0x87 0x4>;
     59			dma-coherent;
     60			clocks = <&sataclk 0>;
     61			phys = <&phy2 0>;
     62			phy-names = "sata-phy";
     63		};
     64
     65		sata3: sata@1a800000 {
     66			compatible = "apm,xgene-ahci-pcie";
     67			reg = <0x0 0x1a800000 0x0 0x1000>,
     68			      <0x0 0x1f230000 0x0 0x1000>,
     69			      <0x0 0x1f23d000 0x0 0x1000>,
     70			      <0x0 0x1f23e000 0x0 0x1000>,
     71			      <0x0 0x1f237000 0x0 0x1000>;
     72			interrupts = <0x0 0x88 0x4>;
     73			dma-coherent;
     74			clocks = <&sataclk 0>;
     75			phys = <&phy3 0>;
     76			phy-names = "sata-phy";
     77		};