cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cortina,gemini-sata-bridge.yaml (3024B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Cortina Systems Gemini SATA Bridge
      8
      9maintainers:
     10  - Linus Walleij <linus.walleij@linaro.org>
     11
     12description: |
     13    The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
     14    takes two Faraday Technology FTIDE010 PATA controllers and bridges
     15    them in different configurations to two SATA ports.
     16
     17properties:
     18  compatible:
     19    const: cortina,gemini-sata-bridge
     20
     21  reg:
     22    maxItems: 1
     23
     24  resets:
     25    minItems: 2
     26    maxItems: 2
     27    description: phandles to the reset lines for both SATA bridges
     28
     29  reset-names:
     30    items:
     31      - const: sata0
     32      - const: sata1
     33
     34  clocks:
     35    minItems: 2
     36    maxItems: 2
     37    description: phandles to the compulsory peripheral clocks
     38
     39  clock-names:
     40    items:
     41      - const: SATA0_PCLK
     42      - const: SATA1_PCLK
     43
     44  syscon:
     45    $ref: /schemas/types.yaml#/definitions/phandle
     46    description: a phandle to the global Gemini system controller
     47
     48  cortina,gemini-ata-muxmode:
     49    $ref: /schemas/types.yaml#/definitions/uint32
     50    enum:
     51      - 0
     52      - 1
     53      - 2
     54      - 3
     55    description: |
     56      Tell the desired multiplexing mode for the ATA controller and SATA
     57      bridges.
     58      Mode 0: ata0 master <-> sata0
     59              ata1 master <-> sata1
     60              ata0 slave interface brought out on IDE pads
     61      Mode 1: ata0 master <-> sata0
     62              ata1 master <-> sata1
     63              ata1 slave interface brought out on IDE pads
     64      Mode 2: ata1 master <-> sata1
     65              ata1 slave  <-> sata0
     66              ata0 master and slave interfaces brought out on IDE pads
     67      Mode 3: ata0 master <-> sata0
     68              ata0 slave  <-> sata1
     69              ata1 master and slave interfaces brought out on IDE pads
     70
     71  cortina,gemini-enable-ide-pins:
     72    type: boolean
     73    description: Enables the PATA to IDE connection.
     74      The muxmode setting decides whether ATA0 or ATA1 is brought out,
     75      and whether master, slave or both interfaces get brought out.
     76
     77  cortina,gemini-enable-sata-bridge:
     78    type: boolean
     79    description: Enables the PATA to SATA bridge inside the Gemnini SoC.
     80      The Muxmode decides what PATA blocks will be muxed out and how.
     81
     82required:
     83  - clocks
     84  - clock-names
     85  - cortina,gemini-ata-muxmode
     86  - resets
     87  - reset-names
     88  - compatible
     89  - reg
     90  - syscon
     91
     92additionalProperties: false
     93
     94examples:
     95  - |
     96    #include <dt-bindings/clock/cortina,gemini-clock.h>
     97    sata@46000000 {
     98      compatible = "cortina,gemini-sata-bridge";
     99      reg = <0x46000000 0x100>;
    100      resets = <&rcon 26>, <&rcon 27>;
    101      reset-names = "sata0", "sata1";
    102      clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
    103               <&gcc GEMINI_CLK_GATE_SATA1>;
    104      clock-names = "SATA0_PCLK", "SATA1_PCLK";
    105      syscon = <&syscon>;
    106      cortina,gemini-ata-muxmode = <3>;
    107      cortina,gemini-enable-ide-pins;
    108      cortina,gemini-enable-sata-bridge;
    109    };