cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sata_highbank.yaml (2589B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Calxeda AHCI SATA Controller
      8
      9description: |
     10  The Calxeda SATA controller mostly conforms to the AHCI interface
     11  with some special extensions to add functionality, to map GPIOs for
     12  activity LEDs and for mapping the ComboPHYs.
     13
     14maintainers:
     15  - Andre Przywara <andre.przywara@arm.com>
     16
     17properties:
     18  compatible:
     19    const: calxeda,hb-ahci
     20
     21  reg:
     22    maxItems: 1
     23
     24  interrupts:
     25    maxItems: 1
     26
     27  dma-coherent: true
     28
     29  calxeda,pre-clocks:
     30    $ref: /schemas/types.yaml#/definitions/uint32
     31    description: |
     32      Indicates the number of additional clock cycles to transmit before
     33      sending an SGPIO pattern.
     34
     35  calxeda,post-clocks:
     36    $ref: /schemas/types.yaml#/definitions/uint32
     37    description: |
     38      Indicates the number of additional clock cycles to transmit after
     39      sending an SGPIO pattern.
     40
     41  calxeda,led-order:
     42    description: Maps port numbers to offsets within the SGPIO bitstream.
     43    $ref: /schemas/types.yaml#/definitions/uint32-array
     44    minItems: 1
     45    maxItems: 8
     46
     47  calxeda,port-phys:
     48    description: |
     49      phandle-combophy and lane assignment, which maps each SATA port to a
     50      combophy and a lane within that combophy
     51    $ref: /schemas/types.yaml#/definitions/phandle-array
     52    minItems: 1
     53    maxItems: 8
     54    items:
     55      minItems: 2
     56      maxItems: 2
     57
     58  calxeda,tx-atten:
     59    description: |
     60      Contains TX attenuation override codes, one per port.
     61      The upper 24 bits of each entry are always 0 and thus ignored.
     62    $ref: /schemas/types.yaml#/definitions/uint32-array
     63    minItems: 1
     64    maxItems: 8
     65
     66  calxeda,sgpio-gpio:
     67    maxItems: 3
     68    description: |
     69      phandle-gpio bank, bit offset, and default on or off, which indicates
     70      that the driver supports SGPIO indicator lights using the indicated
     71      GPIOs.
     72
     73required:
     74  - compatible
     75  - reg
     76  - interrupts
     77
     78additionalProperties: false
     79
     80examples:
     81  - |
     82    sata@ffe08000 {
     83        compatible = "calxeda,hb-ahci";
     84        reg = <0xffe08000 0x1000>;
     85        interrupts = <115>;
     86        dma-coherent;
     87        calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
     88                             <&combophy0 2>, <&combophy0 3>;
     89        calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
     90        calxeda,led-order = <4 0 1 2 3>;
     91        calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
     92        calxeda,pre-clocks = <10>;
     93        calxeda,post-clocks = <0>;
     94    };
     95
     96...