cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun8i-a23-rsb.yaml (1403B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/bus/allwinner,sun8i-a23-rsb.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A23 RSB Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  "#address-cells":
     15    const: 1
     16
     17  "#size-cells":
     18    const: 0
     19
     20  compatible:
     21    oneOf:
     22      - const: allwinner,sun8i-a23-rsb
     23      - items:
     24          - enum:
     25              - allwinner,sun8i-a83t-rsb
     26              - allwinner,sun50i-h616-rsb
     27          - const: allwinner,sun8i-a23-rsb
     28
     29  reg:
     30    maxItems: 1
     31
     32  interrupts:
     33    maxItems: 1
     34
     35  clocks:
     36    maxItems: 1
     37
     38  resets:
     39    maxItems: 1
     40
     41  clock-frequency:
     42    minimum: 1
     43    maximum: 20000000
     44
     45patternProperties:
     46  "^.*@[0-9a-fA-F]+$":
     47    type: object
     48    properties:
     49      reg:
     50        maxItems: 1
     51
     52    required:
     53      - reg
     54
     55required:
     56  - compatible
     57  - reg
     58  - interrupts
     59  - clocks
     60  - resets
     61
     62examples:
     63  - |
     64    rsb@1f03400 {
     65        compatible = "allwinner,sun8i-a23-rsb";
     66        reg = <0x01f03400 0x400>;
     67        interrupts = <0 39 4>;
     68        clocks = <&apb0_gates 3>;
     69        clock-frequency = <3000000>;
     70        resets = <&apb0_rst 3>;
     71        #address-cells = <1>;
     72        #size-cells = <0>;
     73
     74        pmic@3e3 {
     75            reg = <0x3e3>;
     76
     77            /* ... */
     78        };
     79    };
     80
     81additionalProperties: false