cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arm,integrator-ap-lm.yaml (2424B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Integrator/AP Logic Module extension bus
      8
      9maintainers:
     10  - Linus Walleij <linusw@kernel.org>
     11
     12description: The Integrator/AP is a prototyping platform and as such has a
     13  site for stacking up to four logic modules (LM) designed specifically for
     14  use with this platform. A special system controller register can be read to
     15  determine if a logic module is connected at index 0, 1, 2 or 3. The logic
     16  module connector is described in this binding. The logic modules per se
     17  then have their own specific per-module bindings and they will be described
     18  as subnodes under this logic module extension bus.
     19
     20properties:
     21  "#address-cells":
     22    const: 1
     23
     24  "#size-cells":
     25    const: 1
     26
     27  compatible:
     28    items:
     29      - const: arm,integrator-ap-lm
     30
     31  ranges: true
     32  dma-ranges: true
     33
     34patternProperties:
     35  "^bus(@[0-9a-f]*)?$":
     36    description: Nodes on the Logic Module bus represent logic modules
     37      and are named with bus. The first module is at 0xc0000000, the second
     38      at 0xd0000000 and so on until the top of the memory of the system at
     39      0xffffffff. All information about the memory used by the module is
     40      in ranges and dma-ranges.
     41    type: object
     42
     43    required:
     44      - compatible
     45
     46required:
     47  - compatible
     48
     49examples:
     50  - |
     51    bus@c0000000 {
     52      compatible = "arm,integrator-ap-lm";
     53      #address-cells = <1>;
     54      #size-cells = <1>;
     55      ranges = <0xc0000000 0xc0000000 0x40000000>;
     56      dma-ranges;
     57
     58      bus@c0000000 {
     59        compatible = "simple-bus";
     60        ranges = <0x00000000 0xc0000000 0x10000000>;
     61        /* The Logic Modules sees the Core Module 0 RAM @80000000 */
     62        dma-ranges = <0x00000000 0x80000000 0x10000000>;
     63        #address-cells = <1>;
     64        #size-cells = <1>;
     65
     66        serial@100000 {
     67          compatible = "arm,pl011", "arm,primecell";
     68          reg = <0x00100000 0x1000>;
     69          interrupts-extended = <&impd1_vic 1>;
     70        };
     71
     72        impd1_vic: interrupt-controller@3000000 {
     73          compatible = "arm,pl192-vic";
     74          interrupt-controller;
     75          #interrupt-cells = <1>;
     76          reg = <0x03000000 0x1000>;
     77          valid-mask = <0x00000bff>;
     78          interrupts-extended = <&pic 9>;
     79        };
     80      };
     81    };
     82
     83additionalProperties: false