cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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moxtet.txt (1342B)


      1Turris Mox module status and configuration bus (over SPI)
      2
      3Required properties:
      4 - compatible		: Should be "cznic,moxtet"
      5 - #address-cells	: Has to be 1
      6 - #size-cells		: Has to be 0
      7 - spi-cpol		: Required inverted clock polarity
      8 - spi-cpha		: Required shifted clock phase
      9 - interrupts		: Must contain reference to the shared interrupt line
     10 - interrupt-controller	: Required
     11 - #interrupt-cells	: Has to be 1
     12
     13For other required and optional properties of SPI slave nodes please refer to
     14../spi/spi-bus.txt.
     15
     16Required properties of subnodes:
     17 - reg			: Should be position on the Moxtet bus (how many Moxtet
     18			  modules are between this module and CPU module, so
     19			  either 0 or a positive integer)
     20
     21The driver finds the devices connected to the bus by itself, but it may be
     22needed to reference some of them from other parts of the device tree. In that
     23case the devices can be defined as subnodes of the moxtet node.
     24
     25Example:
     26
     27	moxtet@1 {
     28		compatible = "cznic,moxtet";
     29		#address-cells = <1>;
     30		#size-cells = <0>;
     31		reg = <1>;
     32		spi-max-frequency = <10000000>;
     33		spi-cpol;
     34		spi-cpha;
     35		interrupt-controller;
     36		#interrupt-cells = <1>;
     37		interrupt-parent = <&gpiosb>;
     38		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
     39
     40		moxtet_sfp: gpio@0 {
     41			compatible = "cznic,moxtet-gpio";
     42			gpio-controller;
     43			#gpio-cells = <2>;
     44			reg = <0>;
     45		}
     46	};