allwinner,sun9i-a80-mmc-config-clk.yaml (1433B)
1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A80 MMC Configuration Clock Device Tree Bindings 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13deprecated: true 14 15description: > 16 There is one clock/reset output per mmc controller. The number of 17 outputs is determined by the size of the address block, which is 18 related to the overall mmc block. 19 20properties: 21 "#clock-cells": 22 const: 1 23 description: > 24 The additional ID argument passed to the clock shall refer to 25 the index of the output. 26 27 "#reset-cells": 28 const: 1 29 30 compatible: 31 const: allwinner,sun9i-a80-mmc-config-clk 32 33 reg: 34 maxItems: 1 35 36 clocks: 37 maxItems: 1 38 39 resets: 40 maxItems: 1 41 42 clock-output-names: 43 maxItems: 4 44 45required: 46 - "#clock-cells" 47 - "#reset-cells" 48 - compatible 49 - reg 50 - clocks 51 - clock-output-names 52 53additionalProperties: false 54 55examples: 56 - | 57 clk@1c13000 { 58 #clock-cells = <1>; 59 #reset-cells = <1>; 60 compatible = "allwinner,sun9i-a80-mmc-config-clk"; 61 reg = <0x01c13000 0x10>; 62 clocks = <&ahb0_gates 8>; 63 resets = <&ahb0_resets 8>; 64 clock-output-names = "mmc0_config", "mmc1_config", 65 "mmc2_config", "mmc3_config"; 66 }; 67 68...