cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun9i-a80-usb-phy-clk.yaml (1220B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A80 USB PHY Clock Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13deprecated: true
     14
     15properties:
     16  "#clock-cells":
     17    const: 1
     18    description: >
     19      The additional ID argument passed to the clock shall refer to
     20      the index of the output.
     21
     22  "#reset-cells":
     23    const: 1
     24
     25  compatible:
     26    const: allwinner,sun9i-a80-usb-phy-clk
     27
     28  reg:
     29    maxItems: 1
     30
     31  clocks:
     32    maxItems: 1
     33
     34  clock-output-names:
     35    maxItems: 6
     36
     37required:
     38  - "#clock-cells"
     39  - "#reset-cells"
     40  - compatible
     41  - reg
     42  - clocks
     43  - clock-output-names
     44
     45additionalProperties: false
     46
     47examples:
     48  - |
     49    clk@a08004 {
     50        #clock-cells = <1>;
     51        #reset-cells = <1>;
     52        compatible = "allwinner,sun9i-a80-usb-phy-clk";
     53        reg = <0x00a08004 0x4>;
     54        clocks = <&ahb1_gates 1>;
     55        clock-output-names = "usb_phy0", "usb_hsic1_480M",
     56                             "usb_phy1", "usb_hsic2_480M",
     57                             "usb_phy2", "usb_hsic_12M";
     58    };
     59
     60...