cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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alphascale,acc.txt (2768B)


      1Alphascale Clock Controller
      2
      3The ACC (Alphascale Clock Controller) is responsible of choising proper
      4clock source, setting deviders and clock gates.
      5
      6Required properties for the ACC node:
      7 - compatible: must be "alphascale,asm9260-clock-controller"
      8 - reg: must contain the ACC register base and size
      9 - #clock-cells : shall be set to 1.
     10
     11Simple one-cell clock specifier format is used, where the only cell is used
     12as an index of the clock inside the provider.
     13It is encouraged to use dt-binding for clock index definitions. SoC specific
     14dt-binding should be included to the device tree descriptor. For example
     15Alphascale ASM9260:
     16#include <dt-bindings/clock/alphascale,asm9260.h>
     17
     18This binding contains two types of clock providers:
     19 _AHB_ - AHB gate;
     20 _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
     21All clock specific details can be found in the SoC documentation.
     22CLKID_AHB_ROM		0
     23CLKID_AHB_RAM		1
     24CLKID_AHB_GPIO		2
     25CLKID_AHB_MAC		3
     26CLKID_AHB_EMI		4
     27CLKID_AHB_USB0		5
     28CLKID_AHB_USB1		6
     29CLKID_AHB_DMA0		7
     30CLKID_AHB_DMA1		8
     31CLKID_AHB_UART0		9
     32CLKID_AHB_UART1		10
     33CLKID_AHB_UART2		11
     34CLKID_AHB_UART3		12
     35CLKID_AHB_UART4		13
     36CLKID_AHB_UART5		14
     37CLKID_AHB_UART6		15
     38CLKID_AHB_UART7		16
     39CLKID_AHB_UART8		17
     40CLKID_AHB_UART9		18
     41CLKID_AHB_I2S0		19
     42CLKID_AHB_I2C0		20
     43CLKID_AHB_I2C1		21
     44CLKID_AHB_SSP0		22
     45CLKID_AHB_IOCONFIG	23
     46CLKID_AHB_WDT		24
     47CLKID_AHB_CAN0		25
     48CLKID_AHB_CAN1		26
     49CLKID_AHB_MPWM		27
     50CLKID_AHB_SPI0		28
     51CLKID_AHB_SPI1		29
     52CLKID_AHB_QEI		30
     53CLKID_AHB_QUADSPI0	31
     54CLKID_AHB_CAMIF		32
     55CLKID_AHB_LCDIF		33
     56CLKID_AHB_TIMER0	34
     57CLKID_AHB_TIMER1	35
     58CLKID_AHB_TIMER2	36
     59CLKID_AHB_TIMER3	37
     60CLKID_AHB_IRQ		38
     61CLKID_AHB_RTC		39
     62CLKID_AHB_NAND		40
     63CLKID_AHB_ADC0		41
     64CLKID_AHB_LED		42
     65CLKID_AHB_DAC0		43
     66CLKID_AHB_LCD		44
     67CLKID_AHB_I2S1		45
     68CLKID_AHB_MAC1		46
     69
     70CLKID_SYS_CPU		47
     71CLKID_SYS_AHB		48
     72CLKID_SYS_I2S0M		49
     73CLKID_SYS_I2S0S		50
     74CLKID_SYS_I2S1M		51
     75CLKID_SYS_I2S1S		52
     76CLKID_SYS_UART0		53
     77CLKID_SYS_UART1		54
     78CLKID_SYS_UART2		55
     79CLKID_SYS_UART3		56
     80CLKID_SYS_UART4		56
     81CLKID_SYS_UART5		57
     82CLKID_SYS_UART6		58
     83CLKID_SYS_UART7		59
     84CLKID_SYS_UART8		60
     85CLKID_SYS_UART9		61
     86CLKID_SYS_SPI0		62
     87CLKID_SYS_SPI1		63
     88CLKID_SYS_QUADSPI	64
     89CLKID_SYS_SSP0		65
     90CLKID_SYS_NAND		66
     91CLKID_SYS_TRACE		67
     92CLKID_SYS_CAMM		68
     93CLKID_SYS_WDT		69
     94CLKID_SYS_CLKOUT	70
     95CLKID_SYS_MAC		71
     96CLKID_SYS_LCD		72
     97CLKID_SYS_ADCANA	73
     98
     99Example of clock consumer with _SYS_ and _AHB_ sinks.
    100uart4: serial@80010000 {
    101	compatible = "alphascale,asm9260-uart";
    102	reg = <0x80010000 0x4000>;
    103	clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
    104	interrupts = <19>;
    105};
    106
    107Clock consumer with only one, _AHB_ sink.
    108timer0: timer@80088000 {
    109	compatible = "alphascale,asm9260-timer";
    110	reg = <0x80088000 0x4000>;
    111	clocks = <&acc CLKID_AHB_TIMER0>;
    112	interrupts = <29>;
    113};
    114