cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amlogic,gxbb-clkc.txt (1620B)


      1* Amlogic GXBB Clock and Reset Unit
      2
      3The Amlogic GXBB clock controller generates and supplies clock to various
      4controllers within the SoC.
      5
      6Required Properties:
      7
      8- compatible: should be:
      9		"amlogic,gxbb-clkc" for GXBB SoC,
     10		"amlogic,gxl-clkc" for GXL and GXM SoC,
     11		"amlogic,axg-clkc" for AXG SoC.
     12		"amlogic,g12a-clkc" for G12A SoC.
     13		"amlogic,g12b-clkc" for G12B SoC.
     14		"amlogic,sm1-clkc" for SM1 SoC.
     15- clocks : list of clock phandle, one for each entry clock-names.
     16- clock-names : should contain the following:
     17  * "xtal": the platform xtal
     18
     19- #clock-cells: should be 1.
     20
     21Each clock is assigned an identifier and client nodes can use this identifier
     22to specify the clock which they consume. All available clocks are defined as
     23preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
     24used in device tree sources.
     25
     26Parent node should have the following properties :
     27- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
     28              "amlogic,meson-axg-hhi-sysctrl"
     29- reg: base address and size of the HHI system control register space.
     30
     31Example: Clock controller node:
     32
     33sysctrl: system-controller@0 {
     34	compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
     35	reg = <0 0 0 0x400>;
     36
     37	clkc: clock-controller {
     38		#clock-cells = <1>;
     39		compatible = "amlogic,gxbb-clkc";
     40		clocks = <&xtal>;
     41		clock-names = "xtal";
     42	};
     43};
     44
     45Example: UART controller node that consumes the clock generated by the clock
     46  controller:
     47
     48	uart_AO: serial@c81004c0 {
     49		compatible = "amlogic,meson-uart";
     50		reg = <0xc81004c0 0x14>;
     51		interrupts = <0 90 1>;
     52		clocks = <&clkc CLKID_CLK81>;
     53	};