cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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artpec6.txt (1271B)


      1* Clock bindings for Axis ARTPEC-6 chip
      2
      3The bindings are based on the clock provider binding in
      4Documentation/devicetree/bindings/clock/clock-bindings.txt
      5
      6External clocks:
      7----------------
      8
      9There are two external inputs to the main clock controller which should be
     10provided using the common clock bindings.
     11- "sys_refclk": External 50 Mhz oscillator (required)
     12- "i2s_refclk": Alternate audio reference clock (optional).
     13
     14Main clock controller
     15---------------------
     16
     17Required properties:
     18- #clock-cells: Should be <1>
     19  See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
     20- compatible: Should be "axis,artpec6-clkctrl"
     21- reg: Must contain the base address and length of the system controller
     22- clocks:  Must contain a phandle entry for each clock in clock-names
     23- clock-names: Must include the external oscillator ("sys_refclk"). Optional
     24  ones are the audio reference clock ("i2s_refclk") and the audio fractional
     25  dividers ("frac_clk0" and "frac_clk1").
     26
     27Examples:
     28
     29ext_clk: ext_clk {
     30	#clock-cells = <0>;
     31	compatible = "fixed-clock";
     32	clock-frequency = <50000000>;
     33};
     34
     35clkctrl: clkctrl@f8000000 {
     36	#clock-cells = <1>;
     37	compatible = "axis,artpec6-clkctrl";
     38	reg = <0xf8000000 0x48>;
     39	clocks = <&ext_clk>;
     40	clock-names = "sys_refclk";
     41};