cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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calxeda.yaml (1900B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/calxeda.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Device Tree Clock bindings for Calxeda highbank platform
      8
      9description: |
     10  This binding covers the Calxeda SoC internal peripheral and bus clocks
     11  as used by peripherals. The clocks live inside the "system register"
     12  region of the SoC, so are typically presented as children of an
     13  "hb-sregs" node.
     14
     15maintainers:
     16  - Andre Przywara <andre.przywara@arm.com>
     17
     18properties:
     19  "#clock-cells":
     20    const: 0
     21
     22  compatible:
     23    enum:
     24      - calxeda,hb-pll-clock
     25      - calxeda,hb-a9periph-clock
     26      - calxeda,hb-a9bus-clock
     27      - calxeda,hb-emmc-clock
     28
     29  reg:
     30    maxItems: 1
     31
     32  clocks:
     33    maxItems: 1
     34
     35required:
     36  - "#clock-cells"
     37  - compatible
     38  - clocks
     39  - reg
     40
     41additionalProperties: false
     42
     43examples:
     44  - |
     45    sregs@3fffc000 {
     46        compatible = "calxeda,hb-sregs";
     47        reg = <0x3fffc000 0x1000>;
     48
     49        clocks {
     50            #address-cells = <1>;
     51            #size-cells = <0>;
     52
     53            osc: oscillator {
     54                #clock-cells = <0>;
     55                compatible = "fixed-clock";
     56                clock-frequency = <33333000>;
     57            };
     58
     59            ddrpll: ddrpll@108 {
     60                #clock-cells = <0>;
     61                compatible = "calxeda,hb-pll-clock";
     62                clocks = <&osc>;
     63                reg = <0x108>;
     64            };
     65
     66            a9pll: a9pll@100 {
     67                #clock-cells = <0>;
     68                compatible = "calxeda,hb-pll-clock";
     69                clocks = <&osc>;
     70                reg = <0x100>;
     71            };
     72
     73            a9periphclk: a9periphclk@104 {
     74                #clock-cells = <0>;
     75                compatible = "calxeda,hb-a9periph-clock";
     76                clocks = <&a9pll>;
     77                reg = <0x104>;
     78            };
     79        };
     80    };
     81
     82...