cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,flexspi-clock.yaml (1075B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale FlexSPI clock driver for Layerscape SoCs
      8
      9maintainers:
     10  - Michael Walle <michael@walle.cc>
     11
     12description:
     13  The Freescale Layerscape SoCs have a special FlexSPI clock which is
     14  derived from the platform PLL.
     15
     16properties:
     17  compatible:
     18    enum:
     19      - fsl,ls1028a-flexspi-clk
     20      - fsl,lx2160a-flexspi-clk
     21
     22  reg:
     23    maxItems: 1
     24
     25  clocks:
     26    maxItems: 1
     27
     28  '#clock-cells':
     29    const: 0
     30
     31  clock-output-names:
     32    maxItems: 1
     33
     34required:
     35  - compatible
     36  - reg
     37  - clocks
     38  - '#clock-cells'
     39
     40additionalProperties: false
     41
     42examples:
     43  - |
     44    dcfg {
     45        #address-cells = <1>;
     46        #size-cells = <1>;
     47
     48        fspi_clk: clock-controller@900 {
     49            compatible = "fsl,ls1028a-flexspi-clk";
     50            reg = <0x900 0x4>;
     51            #clock-cells = <0>;
     52            clocks = <&parentclk>;
     53            clock-output-names = "fspi_clk";
     54        };
     55    };