cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,plldig.yaml (1400B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
      8
      9maintainers:
     10  - Wen He <wen.he_1@nxp.com>
     11
     12description: |
     13  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
     14  interface in the display core, as implemented in TSMC CLN28HPM PLL.
     15  which generate and offers pixel clocks to Display.
     16
     17properties:
     18  compatible:
     19    const: fsl,ls1028a-plldig
     20
     21  reg:
     22    maxItems: 1
     23
     24  clocks:
     25    maxItems: 1
     26
     27  '#clock-cells':
     28    const: 0
     29
     30  fsl,vco-hz:
     31    description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
     32      of this PLL cannot be changed during runtime only at startup. Therefore,
     33      the output frequencies are very limited and might not even closely match
     34      the requested frequency. To work around this restriction the user may specify
     35      its own desired VCO frequency for the PLL.
     36    minimum: 650000000
     37    maximum: 1300000000
     38    default: 1188000000
     39
     40required:
     41  - compatible
     42  - reg
     43  - clocks
     44  - '#clock-cells'
     45
     46additionalProperties: false
     47
     48examples:
     49  # Display PIXEL Clock node:
     50  - |
     51    dpclk: clock-display@f1f0000 {
     52        compatible = "fsl,ls1028a-plldig";
     53        reg = <0xf1f0000 0xffff>;
     54        #clock-cells = <0>;
     55        clocks = <&osc_27m>;
     56    };
     57
     58...