cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,sai-clock.yaml (1332B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale SAI bitclock-as-a-clock binding
      8
      9maintainers:
     10  - Michael Walle <michael@walle.cc>
     11
     12description: |
     13  It is possible to use the BCLK pin of a SAI module as a generic clock
     14  output. Some SoC are very constrained in their pin multiplexer
     15  configuration. Eg. pins can only be changed groups. For example, on the
     16  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
     17  the second pins are wasted. Using this binding it is possible to use the
     18  clock of the second SAI as a MCLK clock for an audio codec, for example.
     19
     20  This is a composite of a gated clock and a divider clock.
     21
     22properties:
     23  compatible:
     24    const: fsl,vf610-sai-clock
     25
     26  reg:
     27    maxItems: 1
     28
     29  clocks:
     30    maxItems: 1
     31
     32  '#clock-cells':
     33    const: 0
     34
     35required:
     36  - compatible
     37  - reg
     38  - clocks
     39  - '#clock-cells'
     40
     41additionalProperties: false
     42
     43examples:
     44  - |
     45    soc {
     46        #address-cells = <2>;
     47        #size-cells = <2>;
     48
     49        mclk: clock-mclk@f130080 {
     50            compatible = "fsl,vf610-sai-clock";
     51            reg = <0x0 0xf130080 0x0 0x80>;
     52            #clock-cells = <0>;
     53            clocks = <&parentclk>;
     54        };
     55    };