cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

hi3660-clock.txt (1362B)

      1* Hisilicon Hi3660 Clock Controller
      2
      3The Hi3660 clock controller generates and supplies clock to various
      4controllers within the Hi3660 SoC.
      5
      6Required Properties:
      7
      8- compatible: the compatible should be one of the following strings to
      9	indicate the clock controller functionality.
     10
     11	- "hisilicon,hi3660-crgctrl"
     12	- "hisilicon,hi3660-pctrl"
     13	- "hisilicon,hi3660-pmuctrl"
     14	- "hisilicon,hi3660-sctrl"
     15	- "hisilicon,hi3660-iomcu"
     16	- "hisilicon,hi3660-stub-clk"
     17
     18- reg: physical base address of the controller and length of memory mapped
     19  region.
     20
     21- #clock-cells: should be 1.
     22
     23Optional Properties:
     24
     25- mboxes: Phandle to the mailbox for sending message to MCU.
     26            (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
     27
     28Each clock is assigned an identifier and client nodes use this identifier
     29to specify the clock which they consume.
     30
     31All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
     32
     33Examples:
     34	crg_ctrl: clock-controller@fff35000 {
     35		compatible = "hisilicon,hi3660-crgctrl", "syscon";
     36		reg = <0x0 0xfff35000 0x0 0x1000>;
     37		#clock-cells = <1>;
     38	};
     39
     40	uart0: serial@fdf02000 {
     41		compatible = "arm,pl011", "arm,primecell";
     42		reg = <0x0 0xfdf02000 0x0 0x1000>;
     43		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
     44		clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
     45			 <&crg_ctrl HI3660_PCLK>;
     46		clock-names = "uartclk", "apb_pclk";
     47	};