cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hi3670-clock.txt (1241B)

      1* Hisilicon Hi3670 Clock Controller
      2
      3The Hi3670 clock controller generates and supplies clock to various
      4controllers within the Hi3670 SoC.
      5
      6Required Properties:
      7
      8- compatible: the compatible should be one of the following strings to
      9	indicate the clock controller functionality.
     10
     11	- "hisilicon,hi3670-crgctrl"
     12	- "hisilicon,hi3670-pctrl"
     13	- "hisilicon,hi3670-pmuctrl"
     14	- "hisilicon,hi3670-sctrl"
     15	- "hisilicon,hi3670-iomcu"
     16	- "hisilicon,hi3670-media1-crg"
     17	- "hisilicon,hi3670-media2-crg"
     18
     19- reg: physical base address of the controller and length of memory mapped
     20  region.
     21
     22- #clock-cells: should be 1.
     23
     24Each clock is assigned an identifier and client nodes use this identifier
     25to specify the clock which they consume.
     26
     27All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.
     28
     29Examples:
     30	crg_ctrl: clock-controller@fff35000 {
     31		compatible = "hisilicon,hi3670-crgctrl", "syscon";
     32		reg = <0x0 0xfff35000 0x0 0x1000>;
     33		#clock-cells = <1>;
     34	};
     35
     36	uart0: serial@fdf02000 {
     37		compatible = "arm,pl011", "arm,primecell";
     38		reg = <0x0 0xfdf02000 0x0 0x1000>;
     39		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
     40		clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
     41			 <&crg_ctrl HI3670_PCLK>;
     42		clock-names = "uartclk", "apb_pclk";
     43	};