cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hix5hd2-clock.txt (813B)


      1* Hisilicon Hix5hd2 Clock Controller
      2
      3The hix5hd2 clock controller generates and supplies clock to various
      4controllers within the hix5hd2 SoC.
      5
      6Required Properties:
      7
      8- compatible: should be "hisilicon,hix5hd2-clock"
      9- reg: Address and length of the register set
     10- #clock-cells: Should be <1>
     11
     12Each clock is assigned an identifier and client nodes use this identifier
     13to specify the clock which they consume.
     14
     15All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
     16
     17Examples:
     18	clock: clock@f8a22000 {
     19		compatible = "hisilicon,hix5hd2-clock";
     20		reg = <0xf8a22000 0x1000>;
     21		#clock-cells = <1>;
     22	};
     23
     24	uart0: uart@f8b00000 {
     25		compatible = "arm,pl011", "arm,primecell";
     26		reg = <0xf8b00000 0x1000>;
     27		interrupts = <0 49 4>;
     28		clocks = <&clock HIX5HD2_FIXED_83M>;
     29		clock-names = "apb_pclk";
     30	};