idt,versaclock5.yaml (4982B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators 8 9description: | 10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C 11 clock generators providing from 3 to 12 output clocks. 12 13 When referencing the provided clock in the DT using phandle and clock 14 specifier, the following mapping applies: 15 16 - 5P49V5923: 17 0 -- OUT0_SEL_I2CB 18 1 -- OUT1 19 2 -- OUT2 20 21 - 5P49V5933: 22 0 -- OUT0_SEL_I2CB 23 1 -- OUT1 24 2 -- OUT4 25 26 - other parts: 27 0 -- OUT0_SEL_I2CB 28 1 -- OUT1 29 2 -- OUT2 30 3 -- OUT3 31 4 -- OUT4 32 33 The idt,shutdown and idt,output-enable-active properties control the 34 SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown 35 Register, respectively. Their behavior is summarized by the following 36 table: 37 38 SH SP Output when the SD/OE pin is Low/High 39 == == ===================================== 40 0 0 Active/Inactive 41 0 1 Inactive/Active 42 1 0 Active/Shutdown 43 1 1 Inactive/Shutdown 44 45 The case where SH and SP are both 1 is likely not very interesting. 46 47maintainers: 48 - Luca Ceresoli <luca.ceresoli@bootlin.com> 49 50properties: 51 compatible: 52 enum: 53 - idt,5p49v5923 54 - idt,5p49v5925 55 - idt,5p49v5933 56 - idt,5p49v5935 57 - idt,5p49v6901 58 - idt,5p49v6965 59 60 reg: 61 description: I2C device address 62 enum: [ 0x68, 0x6a ] 63 64 '#clock-cells': 65 const: 1 66 67 clock-names: 68 minItems: 1 69 maxItems: 2 70 items: 71 enum: [ xin, clkin ] 72 clocks: 73 minItems: 1 74 maxItems: 2 75 76 idt,xtal-load-femtofarads: 77 minimum: 9000 78 maximum: 22760 79 description: Optional load capacitor for XTAL1 and XTAL2 80 81 idt,shutdown: 82 $ref: /schemas/types.yaml#/definitions/uint32 83 enum: [0, 1] 84 description: | 85 If 1, this enables the shutdown functionality: the chip will be 86 shut down if the SD/OE pin is driven high. If 0, this disables the 87 shutdown functionality: the chip will never be shut down based on 88 the value of the SD/OE pin. This property corresponds to the SH 89 bit of the Primary Source and Shutdown Register. 90 91 idt,output-enable-active: 92 $ref: /schemas/types.yaml#/definitions/uint32 93 enum: [0, 1] 94 description: | 95 If 1, this enables output when the SD/OE pin is high, and disables 96 output when the SD/OE pin is low. If 0, this disables output when 97 the SD/OE pin is high, and enables output when the SD/OE pin is 98 low. This corresponds to the SP bit of the Primary Source and 99 Shutdown Register. 100 101patternProperties: 102 "^OUT[1-4]$": 103 type: object 104 description: 105 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output 106 Configuration" in the Versaclock 5/6/6E Family Register Description 107 and Programming Guide. 108 properties: 109 idt,mode: 110 description: 111 The output drive mode. Values defined in dt-bindings/clk/versaclock.h 112 $ref: /schemas/types.yaml#/definitions/uint32 113 minimum: 0 114 maximum: 6 115 idt,voltage-microvolt: 116 description: The output drive voltage. 117 enum: [ 1800000, 2500000, 3300000 ] 118 idt,slew-percent: 119 description: The Slew rate control for CMOS single-ended. 120 enum: [ 80, 85, 90, 100 ] 121 additionalProperties: false 122 123required: 124 - compatible 125 - reg 126 - '#clock-cells' 127 - idt,shutdown 128 - idt,output-enable-active 129 130allOf: 131 - if: 132 properties: 133 compatible: 134 enum: 135 - idt,5p49v5933 136 - idt,5p49v5935 137 then: 138 # Devices with builtin crystal + optional external input 139 properties: 140 clock-names: 141 const: clkin 142 clocks: 143 maxItems: 1 144 else: 145 # Devices without builtin crystal 146 required: 147 - clock-names 148 - clocks 149 150additionalProperties: false 151 152examples: 153 - | 154 #include <dt-bindings/clk/versaclock.h> 155 156 /* 25MHz reference crystal */ 157 ref25: ref25m { 158 compatible = "fixed-clock"; 159 #clock-cells = <0>; 160 clock-frequency = <25000000>; 161 }; 162 163 i2c@0 { 164 reg = <0x0 0x100>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 /* IDT 5P49V5923 I2C clock generator */ 169 vc5: clock-generator@6a { 170 compatible = "idt,5p49v5923"; 171 reg = <0x6a>; 172 #clock-cells = <1>; 173 174 /* Connect XIN input to 25MHz reference */ 175 clocks = <&ref25m>; 176 clock-names = "xin"; 177 178 /* Set the SD/OE pin's settings */ 179 idt,shutdown = <0>; 180 idt,output-enable-active = <0>; 181 182 OUT1 { 183 idt,mode = <VC5_CMOSD>; 184 idt,voltage-microvolt = <1800000>; 185 idt,slew-percent = <80>; 186 }; 187 188 OUT4 { 189 idt,mode = <VC5_LVDS>; 190 }; 191 }; 192 }; 193 194...