cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx5-clock.yaml (1420B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/imx5-clock.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Clock bindings for Freescale i.MX5
      8
      9maintainers:
     10  - Fabio Estevam <festevam@gmail.com>
     11
     12description: |
     13  The clock consumer should specify the desired clock by having the clock
     14  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
     15  for the full list of i.MX5 clock IDs.
     16
     17properties:
     18  compatible:
     19    enum:
     20      - fsl,imx53-ccm
     21      - fsl,imx51-ccm
     22      - fsl,imx50-ccm
     23
     24  reg:
     25    maxItems: 1
     26
     27  interrupts:
     28    description: CCM provides 2 interrupt requests, request 1 is to generate
     29      interrupt for frequency or mux change, request 2 is to generate
     30      interrupt for oscillator read or PLL lock.
     31    items:
     32      - description: CCM interrupt request 1
     33      - description: CCM interrupt request 2
     34
     35  '#clock-cells':
     36    const: 1
     37
     38required:
     39  - compatible
     40  - reg
     41  - interrupts
     42  - '#clock-cells'
     43
     44additionalProperties: false
     45
     46examples:
     47  - |
     48    #include <dt-bindings/clock/imx5-clock.h>
     49    #include <dt-bindings/interrupt-controller/arm-gic.h>
     50
     51    clock-controller@53fd4000{
     52        compatible = "fsl,imx53-ccm";
     53        reg = <0x53fd4000 0x4000>;
     54        interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
     55                     <0 72 IRQ_TYPE_LEVEL_HIGH>;
     56        #clock-cells = <1>;
     57    };
     58...