cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel,cgu-lgm.yaml (1073B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
      8
      9maintainers:
     10  - Rahul Tanwar <rahul.tanwar@linux.intel.com>
     11
     12description: |
     13  Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
     14  all means to access the CGU hardware module in order to generate a series
     15  of clocks for the whole system and individual peripherals.
     16
     17  Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
     18  defines all available clocks as macros. These macros can be used in device
     19  tree sources.
     20
     21properties:
     22  compatible:
     23    const: intel,cgu-lgm
     24
     25  reg:
     26    maxItems: 1
     27
     28  '#clock-cells':
     29    const: 1
     30
     31required:
     32  - compatible
     33  - reg
     34  - '#clock-cells'
     35
     36additionalProperties: false
     37
     38examples:
     39  - |
     40    cgu: clock-controller@e0200000 {
     41        compatible = "intel,cgu-lgm";
     42        reg = <0xe0200000 0x33c>;
     43        #clock-cells = <1>;
     44    };
     45
     46...