cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel,easic-n5x.yaml (903B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Intel SoCFPGA eASIC N5X platform clock controller binding
      8
      9maintainers:
     10  - Dinh Nguyen <dinguyen@kernel.org>
     11
     12description:
     13  The Intel eASIC N5X Clock controller is an integrated clock controller, which
     14  generates and supplies to all modules.
     15
     16properties:
     17  compatible:
     18    const: intel,easic-n5x-clkmgr
     19
     20  '#clock-cells':
     21    const: 1
     22
     23  reg:
     24    maxItems: 1
     25
     26  clocks:
     27    maxItems: 1
     28
     29required:
     30  - compatible
     31  - reg
     32  - clocks
     33  - '#clock-cells'
     34
     35additionalProperties: false
     36
     37examples:
     38  # Clock controller node:
     39  - |
     40    clkmgr: clock-controller@ffd10000 {
     41      compatible = "intel,easic-n5x-clkmgr";
     42      reg = <0xffd10000 0x1000>;
     43      clocks = <&osc1>;
     44      #clock-cells = <1>;
     45    };
     46...