cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,mmp2-clock.yaml (1553B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Marvell MMP2 and MMP3 Clock Controller
      8
      9maintainers:
     10  - Lubomir Rintel <lkundrak@v3.sk>
     11
     12description: |
     13  The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
     14  controllers within the SoC.
     15
     16  Each clock is assigned an identifier and client nodes use this identifier
     17  to specify the clock which they consume.
     18
     19  All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
     20
     21properties:
     22  compatible:
     23    enum:
     24      - marvell,mmp2-clock # controller compatible with MMP2 SoC
     25      - marvell,mmp3-clock # controller compatible with MMP3 SoC
     26
     27  reg:
     28    items:
     29      - description: MPMU register region
     30      - description: APMU register region
     31      - description: APBC register region
     32
     33  reg-names:
     34    items:
     35      - const: mpmu
     36      - const: apmu
     37      - const: apbc
     38
     39  '#clock-cells':
     40    const: 1
     41
     42  '#reset-cells':
     43    const: 1
     44
     45  '#power-domain-cells':
     46    const: 1
     47
     48required:
     49  - compatible
     50  - reg
     51  - reg-names
     52  - '#clock-cells'
     53  - '#reset-cells'
     54  - '#power-domain-cells'
     55
     56additionalProperties: false
     57
     58examples:
     59  - |
     60    clock-controller@d4050000 {
     61      compatible = "marvell,mmp2-clock";
     62      reg = <0xd4050000 0x1000>,
     63            <0xd4282800 0x400>,
     64            <0xd4015000 0x1000>;
     65      reg-names = "mpmu", "apmu", "apbc";
     66      #clock-cells = <1>;
     67      #reset-cells = <1>;
     68      #power-domain-cells = <1>;
     69    };