cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,pxa910.txt (743B)


      1* Marvell PXA910 Clock Controller
      2
      3The PXA910 clock subsystem generates and supplies clock to various
      4controllers within the PXA910 SoC.
      5
      6Required Properties:
      7
      8- compatible: should be one of the following.
      9  - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
     10
     11- reg: physical base address of the clock subsystem and length of memory mapped
     12  region. There are 4 places in SOC has clock control logic:
     13  "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
     14
     15- #clock-cells: should be 1.
     16- #reset-cells: should be 1.
     17
     18Each clock is assigned an identifier and client nodes use this identifier
     19to specify the clock which they consume.
     20
     21All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.