cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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microchip,pic32.txt (1118B)

      1Microchip PIC32 Clock Controller Binding
      2----------------------------------------
      3Microchip clock controller is consists of few oscillators, PLL, multiplexer
      4and few divider modules.
      5
      6This binding uses common clock bindings.
      7[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
      8
      9Required properties:
     10- compatible: shall be "microchip,pic32mzda-clk".
     11- reg: shall contain base address and length of clock registers.
     12- #clock-cells: shall be 1.
     13
     14Optional properties:
     15- microchip,pic32mzda-sosc: shall be added only if platform has
     16  secondary oscillator connected.
     17
     18Example:
     19	rootclk: clock-controller@1f801200 {
     20		compatible = "microchip,pic32mzda-clk";
     21		reg = <0x1f801200 0x200>;
     22		#clock-cells = <1>;
     23		/* optional */
     24		microchip,pic32mzda-sosc;
     25	};
     26
     27
     28The clock consumer shall specify the desired clock-output of the clock
     29controller (as defined in [2]) by specifying output-id in its "clock"
     30phandle cell.
     31[2] include/dt-bindings/clock/microchip,pic32-clock.h
     32
     33For example for UART2:
     34uart2: serial@2 {
     35	compatible = "microchip,pic32mzda-uart";
     36	reg = <>;
     37	interrupts = <>;
     38	clocks = <&rootclk PB2CLK>;
     39};