cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mvebu-corediv-clock.txt (722B)


      1* Core Divider Clock bindings for Marvell MVEBU SoCs
      2
      3The following is a list of provided IDs and clock names on Armada 370/XP:
      4 0 = nand (NAND clock)
      5
      6Required properties:
      7- compatible : must be "marvell,armada-370-corediv-clock",
      8		       "marvell,armada-375-corediv-clock",
      9		       "marvell,armada-380-corediv-clock",
     10                       "marvell,mv98dx3236-corediv-clock",
     11
     12- reg : must be the register address of Core Divider control register
     13- #clock-cells : from common clock binding; shall be set to 1
     14- clocks : must be set to the parent's phandle
     15
     16Example:
     17
     18corediv_clk: corediv-clocks@18740 {
     19	compatible = "marvell,armada-370-corediv-clock";
     20	reg = <0x18740 0xc>;
     21	#clock-cells = <1>;
     22	clocks = <&pll>;
     23};