cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mvebu-gated-clock.txt (5345B)


      1* Gated Clock bindings for Marvell EBU SoCs
      2
      3Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
      4peripheral clocks to be gated to save some power. The clock consumer
      5should specify the desired clock by having the clock ID in its
      6"clocks" phandle cell. The clock ID is directly mapped to the
      7corresponding clock gating control bit in HW to ease manual clock
      8lookup in datasheet.
      9
     10The following is a list of provided IDs for Armada 370:
     11ID	Clock	Peripheral
     12-----------------------------------
     130	Audio	AC97 Cntrl
     141	pex0_en	PCIe 0 Clock out
     152	pex1_en	PCIe 1 Clock out
     163	ge1	Gigabit Ethernet 1
     174	ge0	Gigabit Ethernet 0
     185	pex0	PCIe Cntrl 0
     199	pex1	PCIe Cntrl 1
     2015	sata0	SATA Host 0
     2117	sdio	SDHCI Host
     2223	crypto	CESA (crypto engine)
     2325	tdm	Time Division Mplx
     2428	ddr	DDR Cntrl
     2530	sata1	SATA Host 0
     26
     27The following is a list of provided IDs for Armada 375:
     28ID	Clock		Peripheral
     29-----------------------------------
     302	mu		Management Unit
     313	pp		Packet Processor
     324	ptp		PTP
     335	pex0		PCIe 0 Clock out
     346	pex1		PCIe 1 Clock out
     358	audio		Audio Cntrl
     3611	nd_clk		Nand Flash Cntrl
     3714	sata0_link	SATA 0 Link
     3815	sata0_core	SATA 0 Core
     3916	usb3		USB3 Host
     4017	sdio		SDHCI Host
     4118	usb		USB Host
     4219	gop		Gigabit Ethernet MAC
     4320	sata1_link	SATA 1 Link
     4421	sata1_core	SATA 1 Core
     4522	xor0		XOR DMA 0
     4623	xor1		XOR DMA 0
     4724	copro		Coprocessor
     4825	tdm		Time Division Mplx
     4928	crypto0_enc	Cryptographic Unit Port 0 Encryption
     5029	crypto0_core	Cryptographic Unit Port 0 Core
     5130	crypto1_enc	Cryptographic Unit Port 1 Encryption
     5231	crypto1_core	Cryptographic Unit Port 1 Core
     53
     54The following is a list of provided IDs for Armada 380/385:
     55ID	Clock		Peripheral
     56-----------------------------------
     570	audio		Audio
     582	ge2		Gigabit Ethernet 2
     593	ge1		Gigabit Ethernet 1
     604	ge0		Gigabit Ethernet 0
     615	pex1		PCIe 1
     626	pex2		PCIe 2
     637	pex3		PCIe 3
     648	pex0		PCIe 0
     659	usb3h0		USB3 Host 0
     6610	usb3h1		USB3 Host 1
     6711	usb3d		USB3 Device
     6813	bm		Buffer Management
     6914	crypto0z	Cryptographic 0 Z
     7015	sata0		SATA 0
     7116	crypto1z	Cryptographic 1 Z
     7217	sdio		SDIO
     7318	usb2		USB 2
     7421	crypto1		Cryptographic 1
     7522	xor0		XOR 0
     7623	crypto0		Cryptographic 0
     7725	tdm		Time Division Multiplexing
     7828	xor1		XOR 1
     7930	sata1		SATA 1
     80
     81The following is a list of provided IDs for Armada 39x:
     82ID	Clock		Peripheral
     83-----------------------------------
     845	pex1		PCIe 1
     856	pex2		PCIe 2
     867	pex3		PCIe 3
     878	pex0		PCIe 0
     889	usb3h0		USB3 Host 0
     8910	usb3h1		USB3 Host 1
     9015	sata0		SATA 0
     9117	sdio		SDIO
     9222	xor0		XOR 0
     9328	xor1		XOR 1
     94
     95The following is a list of provided IDs for Armada XP:
     96ID	Clock	Peripheral
     97-----------------------------------
     980	audio	Audio Cntrl
     991	ge3	Gigabit Ethernet 3
    1002	ge2	Gigabit Ethernet 2
    1013	ge1	Gigabit Ethernet 1
    1024	ge0	Gigabit Ethernet 0
    1035	pex0	PCIe Cntrl 0
    1046	pex1	PCIe Cntrl 1
    1057	pex2	PCIe Cntrl 2
    1068	pex3	PCIe Cntrl 3
    10713	bp
    10814	sata0lnk
    10915	sata0	SATA Host 0
    11016	lcd	LCD Cntrl
    11117	sdio	SDHCI Host
    11218	usb0	USB Host 0
    11319	usb1	USB Host 1
    11420	usb2	USB Host 2
    11522	xor0	XOR DMA 0
    11623	crypto	CESA engine
    11725	tdm	Time Division Mplx
    11828	xor1	XOR DMA 1
    11929	sata1lnk
    12030	sata1	SATA Host 1
    121
    122The following is a list of provided IDs for 98dx3236:
    123ID	Clock	Peripheral
    124-----------------------------------
    1253	ge1	Gigabit Ethernet 1
    1264	ge0	Gigabit Ethernet 0
    1275	pex0	PCIe Cntrl 0
    12817	sdio	SDHCI Host
    12918	usb0	USB Host 0
    13022	xor0	XOR DMA 0
    131
    132The following is a list of provided IDs for Dove:
    133ID	Clock	Peripheral
    134-----------------------------------
    1350	usb0	USB Host 0
    1361	usb1	USB Host 1
    1372	ge	Gigabit Ethernet
    1383	sata	SATA Host
    1394	pex0	PCIe Cntrl 0
    1405	pex1	PCIe Cntrl 1
    1418	sdio0	SDHCI Host 0
    1429	sdio1	SDHCI Host 1
    14310	nand	NAND Cntrl
    14411	camera	Camera Cntrl
    14512	i2s0	I2S Cntrl 0
    14613	i2s1	I2S Cntrl 1
    14715	crypto	CESA engine
    14821	ac97	AC97 Cntrl
    14922	pdma	Peripheral DMA
    15023	xor0	XOR DMA 0
    15124	xor1	XOR DMA 1
    15230	gephy	Gigabit Ethernel PHY
    153Note: gephy(30) is implemented as a parent clock of ge(2)
    154
    155The following is a list of provided IDs for Kirkwood:
    156ID	Clock	Peripheral
    157-----------------------------------
    1580	ge0	Gigabit Ethernet 0
    1592	pex0	PCIe Cntrl 0
    1603	usb0	USB Host 0
    1614	sdio	SDIO Cntrl
    1625	tsu	Transp. Stream Unit
    1636	dunit	SDRAM Cntrl
    1647	runit	Runit
    1658	xor0	XOR DMA 0
    1669	audio	I2S Cntrl 0
    16714	sata0	SATA Host 0
    16815	sata1	SATA Host 1
    16916	xor1	XOR DMA 1
    17017	crypto	CESA engine
    17118	pex1	PCIe Cntrl 1
    17219	ge1	Gigabit Ethernet 1
    17320	tdm	Time Division Mplx
    174
    175Required properties:
    176- compatible : shall be one of the following:
    177	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
    178	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
    179	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
    180	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
    181	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
    182	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
    183	"marvell,dove-gating-clock" - for Dove SoC clock gating
    184	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
    185- reg : shall be the register address of the Clock Gating Control register
    186- #clock-cells : from common clock binding; shall be set to 1
    187
    188Optional properties:
    189- clocks : default parent clock phandle (e.g. tclk)
    190
    191Example:
    192
    193gate_clk: clock-gating-control@d0038 {
    194	compatible = "marvell,dove-gating-clock";
    195	reg = <0xd0038 0x4>;
    196	/* default parent clock is tclk */
    197	clocks = <&core_clk 0>;
    198	#clock-cells = <1>;
    199};
    200
    201sdio0: sdio@92000 {
    202	compatible = "marvell,dove-sdhci";
    203	/* get clk gate bit 8 (sdio0) */
    204	clocks = <&gate_clk 8>;
    205};