cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,gcc-msm8998.yaml (1869B)

      1# SPDX-License-Identifier: GPL-2.0-only
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
      8
      9maintainers:
     10  - Stephen Boyd <sboyd@kernel.org>
     11  - Taniya Das <tdas@codeaurora.org>
     12
     13description: |
     14  Qualcomm global clock control module which supports the clocks, resets and
     15  power domains on MSM8998.
     16
     17  See also:
     18  - dt-bindings/clock/qcom,gcc-msm8998.h
     19
     20properties:
     21  compatible:
     22    const: qcom,gcc-msm8998
     23
     24  clocks:
     25    items:
     26      - description: Board XO source
     27      - description: Sleep clock source
     28      - description: Audio reference clock (Optional clock)
     29      - description: PLL test clock source (Optional clock)
     30    minItems: 2
     31
     32  clock-names:
     33    items:
     34      - const: xo
     35      - const: sleep_clk
     36      - const: aud_ref_clk # Optional clock
     37      - const: core_bi_pll_test_se # Optional clock
     38    minItems: 2
     39
     40  '#clock-cells':
     41    const: 1
     42
     43  '#reset-cells':
     44    const: 1
     45
     46  '#power-domain-cells':
     47    const: 1
     48
     49  reg:
     50    maxItems: 1
     51
     52  protected-clocks:
     53    description:
     54      Protected clock specifier list as per common clock binding.
     55
     56required:
     57  - compatible
     58  - clocks
     59  - clock-names
     60  - reg
     61  - '#clock-cells'
     62  - '#reset-cells'
     63  - '#power-domain-cells'
     64
     65additionalProperties: false
     66
     67examples:
     68  - |
     69    #include <dt-bindings/clock/qcom,rpmcc.h>
     70    clock-controller@100000 {
     71      compatible = "qcom,gcc-msm8998";
     72      #clock-cells = <1>;
     73      #reset-cells = <1>;
     74      #power-domain-cells = <1>;
     75      reg = <0x00100000 0xb0000>;
     76      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
     77               <&sleep>,
     78               <0>,
     79               <0>;
     80      clock-names = "xo",
     81                    "sleep_clk",
     82                    "aud_ref_clk",
     83                    "core_bi_pll_test_se";
     84    };
     85...